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Form of workJob Description
Role: Sr. Product Test Engineer
Location: Fremont, CA
Type: Contract
Duration: 12 months (w/ possibility of extension)
In search of a talented Senior Product Test Engineer to perform all aspects of product engineering including managing test functions at offshore OSAT (Offshore Assembling Test) locations. This role will report into Senior Engineering Manager for Hardware ATE Test Team in VLSI Engineering Group. The position is located in Fremont, California, US.
Location: Fremont, CA
Type: Contract
Duration: 12 months (w/ possibility of extension)
In search of a talented Senior Product Test Engineer to perform all aspects of product engineering including managing test functions at offshore OSAT (Offshore Assembling Test) locations. This role will report into Senior Engineering Manager for Hardware ATE Test Team in VLSI Engineering Group. The position is located in Fremont, California, US.
Job responsibilities include:
- Manage data collection; analysis and characterization report generation of all products.
- Responsible for timely execution of reliability test plans for all new products.
- Design of reliability hardware working in close coordination with TE.
- Deploying products in to HVM (High Volume Manufacturing) at OSAT locations.
- Release and manage of ATE (Automated Test Experiments) test programs at production test facilities.
- Active management of OSATS; track and report product yields, hardware inventory management, pro-actively develop and implement yield, cycle time improvement initiatives.
- Manage lot disposition system and come up with processes, procedures for systemic issues in production
- High volume test data analysis using data analysis tools.
- Some international travel to OSATS is required.
- Work closely with test development engineers to improve production yield, test related issues and cycle times improvements.
Experience and Education:
- BS degree in EE or equivalent or MS in EE.
- 5+ years of Product Engineering in Semiconductor industry.
- Working knowledge/experience with foundries, subcons.
- Working knowledge of fab processes and effect on test.
- Experience with Statistical Data Processing, DOEs (Design of experiments), problem solving methodologies, demonstrated decision making skills, cost reduction, and yield enhancement is a plus.
- Experience on Verigy 93000 Digital, Mixed Signal or Teradyne UFlex test platform.
- Sound understanding of Semiconductor Design For Test (DFT) techniques such as ATPG, MBIST, loop back testing of high performance serdes etc.
- Excellent English written and oral communication skills.
- Flexibility to attend meetings with global team (Thailand, Taiwan, India and USA) on different time zones.
- Availability to do quarterly trips to Asia.
About Tessolve:
Technological innovation has accelerated at an unprecedented pace in the recent years and so have the disruptions in the sector of Silicon engineering – complex IC development, increasing failures, inadequate facilities for design, development and testing. At Tessolve, we address these disruptions, helping Semiconductor product companies in Semiconductor IC Design, Test & Product Engineering, PCB Design, Failure Analysis and Systems design. An enabler of smooth design and productization of chips, we leverage our in-house infrastructure, quality excellence practices and cost-effective approaches to bring value driven solutions and services. https://tessolve.com/
