Address
Form of workSummary
Apple's growing wireless silicon development team is developing the next generation of wireless silicon! In this role, you'll be responsible for ASIC pre-silicon verification of extremely complex high throughput communication systems. You will develop leading-edge testbenches, enhance advanced methodologies, develop verification plans, debug functional tests, and utilize coverage analytics. You will be in the center of the organization impacting and influencing many cross-functional teams.
Key Qualifications
- Knowledge of ASIC verification simulation and testbench development flows with SystemVerilog and UVM
- Experience with constrained random testing, coverage closure, and RTL / gate simulations
- Experience with scripting in languages such as Python, Perl, Bash or similar
- Experience with communication / networking chips is a plus
- Phenomenal teammate with excellent communication skills and the desire to seek diverse challenges
Description
This role will provide the opportunity to develop testbenches and create directed / constrained random tests, simulate, and debug. There will be regression triaging, along with analyzing coverage, improve flows and run RTL and gate-level functional simulations. You'll also work closely with the design teams to review specifications and architecture, extract features, define verification plan & coverage model.
Education & Experience
Bachelors plus 3 years of relevant experience required.
Apple's growing wireless silicon development team is developing the next generation of wireless silicon! In this role, you'll be responsible for ASIC pre-silicon verification of extremely complex high throughput communication systems. You will develop leading-edge testbenches, enhance advanced methodologies, develop verification plans, debug functional tests, and utilize coverage analytics. You will be in the center of the organization impacting and influencing many cross-functional teams.
Key Qualifications
- Knowledge of ASIC verification simulation and testbench development flows with SystemVerilog and UVM
- Experience with constrained random testing, coverage closure, and RTL / gate simulations
- Experience with scripting in languages such as Python, Perl, Bash or similar
- Experience with communication / networking chips is a plus
- Phenomenal teammate with excellent communication skills and the desire to seek diverse challenges
Description
This role will provide the opportunity to develop testbenches and create directed / constrained random tests, simulate, and debug. There will be regression triaging, along with analyzing coverage, improve flows and run RTL and gate-level functional simulations. You'll also work closely with the design teams to review specifications and architecture, extract features, define verification plan & coverage model.
Education & Experience
Bachelors plus 3 years of relevant experience required.
