Job description
- Develop verification plans in coordination with design leads and architects - Create and maintain verification test bench components and environments - Develop comprehensive constrained random test suites - Run simulations and debug design and environment issues - Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes - Create automated verification flows for block verification - Apply knowledge of hardware description languages (VHDL/Verilog), and logic simulators to verify complex designs - Influence other block and core level engineers to innovate seamless verification flows
Address
Santa Clara, CA
