Rfic Layout Designer

Role: Modem ASIC RFIC Layout Designer

Location: San Jose, CA (Hybrid – 3 Days per week onsite)

Duration: 6+ Months Contract

Client: Samsung Semiconductor

Job ID: 368874

Requirements:

5+ years’ experience in custom RF/analog layout with extensive knowledge on deep sub-micron CMOS (28nm, FINFET’s, etc.)

Knowledgeable on layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing

Must recognize failure prone circuit and layout structures, proactively work with circuit designer for best approach to problems

High-level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.

Familiarity of CADENCE layout tools and Mentor Graphics verification tools.

Excellent communication skills and able to work with cross-functional teams

Experience:

custom RF/analog layout design: 5 years (Preferred)

deep sub-micron CMOS (28nm, FINFET’s, etc.): 5 years (Preferred)

resistors, capacitors, and inductors: 5 years (Preferred)

block-level and top-level floor-planning: 5 years (Preferred)

transistor-level layout of RF and analog circuit blocks: 5 years (Preferred)

baseband filters, and bandgap/bias/LDO: 5 years (Preferred)

CALIBRE DRC, ERC, LVS: 5 years (Preferred)

CADENCE layout tools and Mentor Graphics verification tools: 5 years (Preferred)

Job Types: Full-time, Contract

Pay: $80.00 - $90.00 per hour

Expected hours: 40 per week

Benefits:

• 401(k)
• 401(k) matching
• Dental insurance
• Health insurance
• Life insurance
• Paid time off
• Vision insurance

Schedule:

• 8 hour shift
• Monday to Friday

Experience:

• RFIC Layout Designer: 5 years (Required)
• 28nm: 5 years (Required)
• FinFet: 5 years (Required)
• CALIBRE DRC: 5 years (Required)
• CADENCE layout: 5 years (Required)
• RF and analog circuit blocks: 5 years (Required)

Ability to Relocate:

• San Jose, CA: Relocate before starting work (Required)

Work Location: On the road