Analog Layout Design Engineer

Job Description

Do Something Wonderful!

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people’s digital lives. Come join us and do something wonderful!

Who We Are

We are the Intel CEG DDR Physical Design team driving the future of DDR technologies with Intel. We deliver custom analog and mixed signal Layout Designs for current and next generation DDR designs which are used across Intel's spectrum of products, including client CPUs, Server CPUs, and/or other domains.

Who You Are

You will be designing the layout of sensitive analog components such as receivers, transmitters, and clocking circuitry and be involved in the latest and greatest DDR IO technologies as well as Intel's current and next-generation process nodes.

Responsibilities of the role include, although not limited to:

• Designs complex layouts of analog signal circuits for a given design specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts.
• Designs and analyzes floorplans, power grid, ESD, bumps, and performs all required verification on the analog blocks.
• Performs the floor-planning and detailed signal planning of complex analog circuits to meet performance and electrical requirements (shielding, matching) for critical signals to optimize for area, power, RV, and performance.
• Develops and drives new and innovative Analog Layout methodologies to improve layout productivity and quality.
• Collaborates with analog circuit design, process technology, and package design teams to meet design specifications, plan work, and negotiate layout tradeoffs as needed.
• Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology used in Analog Layout Design.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelor's degree in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS) with 1+ years of industry experience and/or a Master's degree in Electrical Engineering (EE), Computer Engineering (CE) Computer Science (CS) AND

Required coursework or industry experience above must be related to:

• Analog and mixed signal circuit and/or physical design
• Electronic circuit functionality and behaviors
• CMOS and VLSI component design principles

Preferred Qualifications:

• Integrated circuits and electronics
• Engineering problem solving and analytical skills
• Knowledge of CAD layout software i.e. Virtuoso or ICV for verification
• Experience with scripting languages like Python, Perl, TCL etc.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $83,077.00-$124,371.00

• Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

JobType

Hybrid