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Form of workIn this position you will play a key role in contributing to the development of advanced mixed signal layout for low power, high-speed, SERDES, sensors, PLL and other macros to be used in numerous products from high performance data center SOCs to low power consumer SOCs.
You will join a highly collaborative team, and your success will have a significant impact on our products.
Candidate should have an interest in all the "Key Qualifications" listed, and significant experience in some of them.
Key Qualifications:
- At least 5 years of hands on layout design experience
- Experience in layout of high-speed SerDes blocks and PLLs in advanced Fin-FET process
- Experience using layout design and verification tools
- Experience in floor planning, power grid design, signal routing and repeaters
- Good understanding of clock routing and shielding
- Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating
- Ability to learn and ramp on new tools and methodologies
- Ability to estimate realistic schedule, track and report clear progress and status
- Excellent team player and work closely with the circuit design team
Description:
- Layout design of advanced SERDES and other analog and mixed signal macros in deep Sub-Micron Fin-FET technologies
- Tasks include planning and implementing block and top level floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout
- DRC, LVS and other physical verification tools
- Participate in post-layout circuit performance analysis
- Estimate and track schedules
Education:
Layout design diploma or an electrical engineering degree
Base Salary Ranges:
- 4 - 7 years experience: $75,000.00 - $110,000.00
- 8+ years experience: $110,000.00 - $160,000.00
We are an equal opportunity employer and value diversity in our workforce. All employment decisions are made on the basis of qualifications, ability, and business requirements.
