Company

Samsung SemiconductorSee more

addressAddressSan Jose, CA
type Form of workContractor
CategoryInformation Technology

Job description

What You'll Do

Hiring for an ASIC Layout Design Engineer,  you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products, on advanced CMOS processes.

Location:  Hybrid, working onsite at our San Jose office 3 days per week, with the flexibility to work remotely the remainder of your time 

What You Bring

  • 15 + years of experience with chip design field
  • Bachelor's in engineering related field
  • 5+ years experience in custom RF/analog layout with extensive knowledge on deep sub-micron CMOS (28nm, FINFET's, etc.)
  • Knowledgeable on layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing
  • Must recognize failure prone circuit and layout structures, proactively work with circuit designer for best approach to problems
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. (5) Familiarity of CADENCE layout tools and Mentor Graphics verification tools.
  • Excellent communication skills and able to work with cross-functional teams Detailed Description As an RF Layout Designer, you will be responsible for
  • Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.
  • Layout of sensitive analog components including resistors, capacitors, and inductors
  • Block level and top-level layout through full verification flow including RLC extraction, DRC, LVS, and DFM checking
  • Co-work with designers on block level and top-level floor-planning Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling
  • Top-level layout integration and verification, schedule management.
  • You're inclusive, adapting your style to the situation and diverse global norms of our people.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.

W-2 contract position through Eastridge MSP

Refer code: 7852238. Samsung Semiconductor - The previous day - 2024-01-18 07:57

Samsung Semiconductor

San Jose, CA
Jobs feed

Medical Editing Internship (Philly) - Publicis Health

Publicis Groupe

Philadelphia, PA

Machine Operator(Machining) -2nd Shift

Abb Grain

Jonesboro, AR

DaySpring 2024 Summer Internship - Managing Editor

Dayspring Cards Inc

Siloam Springs, AR

Marketing and Brand Strategy Director

Cti Iii Llc

Folsom, CA

Order Filler

Mary Kay

West, TX

Temporary Retirement Distribution Processor

Alerus Financial

Minnesota, United States

Join our team!

Student Intern - Corporate Governance

Wssc Water

Laurel, MD

Business Development | $100k + commission | Fargo, ND

Express Employment Professionals-Fargo

Fargo, ND

Call today for details!

Share jobs with friends

Related jobs

Asic Layout Designer Engineer (Contractor)

Senior Analog Layout Designer ( 5/4/3nm)

Encore Semi, Inc.

Mountain View, CA

2 weeks ago - seen

PCB Layout Designer

Jobot

Irvine, CA

4 weeks ago - seen

Modem ASIC RFIC Layout Designer

Ursus, Inc.

San Jose, CA

4 weeks ago - seen

RFIC Layout Designer

Nubyt, Inc.

$80 - $90 an hour

San Jose, CA

4 weeks ago - seen

Senior Mask Layout Design Engineer

Nvidia Corporation

Santa Clara, CA

a month ago - seen

PCB Layout Designer

Aequor Technologies

Lake Forest, CA

2 months ago - seen

Analog Layout Design Engineer

Intel

$83,077 - $124,371 a year

Santa Clara, CA

2 months ago - seen

Mask Layout Designer, Sr Staff

Qualcomm

Santa Clara, CA

3 months ago - seen

Senior Engineer, Advanced Packaging Silicon Layout Design Engineer

Samsung Semiconductor

San Jose, CA

3 months ago - seen

Analog Layout Design Engineer

Intel Corporation

Folsom, CA

4 months ago - seen

Summer 2024 Intern, Electronics Design Engineering (PCB Layout)

Western Digital

Irvine, CA

4 months ago - seen

SERDES and Mixed-Signal Layout-Mask Designer

Analog Bits

Sunnyvale, CA

4 months ago - seen

Store Layout Designer

The Retail Odyssey Company

San Diego, CA

4 months ago - seen

PCB Designer and Layout Technician

Stellant Systems

Torrance, CA

4 months ago - seen

PCB Layout Design Engineer

Eurofins

Santa Clara, CA

5 months ago - seen

Plant Layout Designer

Kairos Power

Alameda, CA

5 months ago - seen

PCB Layout Designer

II-VI Incorporated

Fremont, CA

5 months ago - seen