Address
Form of work Job Title:Sr Physical Design Engineer
Location: San Jose, CA
POSITION SUMMARY
7-10+ Yrs of experience in doing hands on Physical Design for complete flow of Netlist to GDSII
Preferred Tool experience on Client ICC2, DC, PT, Calibre OR Genus, Innovus, Tempus, Joules and Calibre; working for last 4+ years.
Strong fundamentals on
Physical design including Synthesis, Floorplan, placement, cts, routing, timing closure 7nm, 16nm, 28nm. 5nm geometry will be advantage.
Sound expertise in TclTk, Perl, Shell scripting.
Technically sound & good team player Should have worked on consumer SoC with low power experience.
Overall, he/she need to ensure successful delivery of his block(s) to customers
Must have:
(1) Client ICC, ICC2, PT-PTSI, DC, OR Cadence Genus, Innovus, Voltus, Joules and Calibre
(2) Taking care of Physical design issues like Hierarchical design planning,.
(3) Timing sign off, PnR, Power sign off, ECO execution, Mentor Calibre based LVS-DRC Closure and Sign off).
(4) Working at Geometry at 65, 45, 28nm,16nm, 7nm and below.
(5) This job involves working from customer site.
(6) motivated technical person who wants to grow experience building large ASIC and exposure to work with multi-site team.
Education: Bachelors Degree in Engineering
Location: San Jose, CA
POSITION SUMMARY
7-10+ Yrs of experience in doing hands on Physical Design for complete flow of Netlist to GDSII
Preferred Tool experience on Client ICC2, DC, PT, Calibre OR Genus, Innovus, Tempus, Joules and Calibre; working for last 4+ years.
Strong fundamentals on
Physical design including Synthesis, Floorplan, placement, cts, routing, timing closure 7nm, 16nm, 28nm. 5nm geometry will be advantage.
Sound expertise in TclTk, Perl, Shell scripting.
Technically sound & good team player Should have worked on consumer SoC with low power experience.
Overall, he/she need to ensure successful delivery of his block(s) to customers
Must have:
(1) Client ICC, ICC2, PT-PTSI, DC, OR Cadence Genus, Innovus, Voltus, Joules and Calibre
(2) Taking care of Physical design issues like Hierarchical design planning,.
(3) Timing sign off, PnR, Power sign off, ECO execution, Mentor Calibre based LVS-DRC Closure and Sign off).
(4) Working at Geometry at 65, 45, 28nm,16nm, 7nm and below.
(5) This job involves working from customer site.
(6) motivated technical person who wants to grow experience building large ASIC and exposure to work with multi-site team.
Education: Bachelors Degree in Engineering
