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Form of workJob Description:
As an Astera Labs Physical Design Intern, you will support the Physical Design team with all aspects of Physical Design implementation and verification of Astera Labs's cutting edge SoC for sub-7nm technology node. The Physical Design Intern will support the following areas within the Physical Design team: floor-planning, auto place and route, physical implementation, timing verification, signal integrity analysis, power analysis, formal verification, and physical layout verification at block and/or full chip level.
Basic Qualifications:
- Working towards B.S. or M.S in Electrical Engineering or related field
- 5 GPA or higher
- Self-motivated team worker, good verbal and written communication skills
- Good understanding in VLSI digital design/Layout/Timing closure
- Programming and scripting (Perl, TCL, C++)
- Basic knowledge on circuit design, device delays, and timing at gate-level
Required Experience:
- Prior internship experience in Physical Design
- Project work experience using UNIX
- Familiar with industry EDA tools such as Synopsys ICC/FC/Primetime/ICV, Cadence Innovus
- Hardware Design Languages like Verilog, VHDL
- Solid understanding of hierarchical Physical Design strategies, methodologies and deep sub-micron technology issues
