Senior Digital Integration & Timing Engineer

As a Digital Integration & Timing Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators and multiple ARM-based sub-systems. You will have the opportunity to work closely with SoC architects and IP developers to develop SoCs that meet Apple devices' power, performance, and area goals. You will help define the processes, methods, and tools for designing and implementing these large, complex SoCs. Collaboration with multi-disciplinary groups will be needed to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact on getting leading-edge products out to delight millions of customers. - Full chip and block-level timing constraint and closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation). - Deploy and enhance methodology and flows related to timing constraint verification and timing closure. - Generation of consistent block and full chip timing constraints. - Support digital chip integration work and flows. - Execute low power design and physical synthesis techniques, deploying knowledge of UPF and power intent verification. - Collaborate with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve the tape out success on designs - generally bridging everything between the RTL and PD worlds.