Senior Design For Test Engineer (Dft)

Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. As a Senior Design for Test Engineer in the Silicon Computing Development team, you will lead product structural test solutions in design: From defining the architecture, establishing methodology, executing test logic insertion, ensuring verification coverage, developing patterns, and finally working with Tester engineers to bring up test vectors on silicon. You will be part of a team involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions most efficiently. We are looking for a Senior Design for Test Engineerwith a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions.
Responsibilities

• Own block level DFT arch specification documentation & provide Test solutions for increased coverage, optimal design & lower test time.
• Maintain & enhance existing DFT tools by understanding product needs & tailor solutions for current and upcoming products.
• Develop state of the art SRAM Memory self test & Logic test flows and implementation.
• Implement micro-architectural specifications in Verilog or System Verilog.
• Provide test plans and engage closely with verification engineers to perform waveform reviews.
• Hold a primary role in enabling silicon by working directly with Test Engineers to bring up test vectors, and analyzing yield & diagnosis.

Qualifications
Required Qualifications:

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
• 6 + years of experience about industry standard practice in Silicon Hardware Design for Test - ATPG, JTAG, MBIST, and trade-offs between design cost, test quality and test time.

Other qualifications:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Experience developing Scan architecture & micro-arch specifications as it relates to large SOCs along with scan insertion techniques for IP's like PLL's, IO's & Power circuits.
• Proficient at Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression & retargeting flows - using EDA tools like Mentor Tessent or Synopsys TestMax.
• Knowledge of Verilog or System Verilog with experience using simulators and waveform debugging tools.
• Ability to pioneer flows for Gate-level simulation (GLS), perform coverage analysis, and debug for achieving high fault coverage.
• Experience with Static Timing Analysis & constraint generation.
• Experience with ATE and Silicon bring-up with proficiency in Mentor Tessent / Synopsys tools for Yield & Diagnosis.
• Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable.
• Proficient in scripting languages (Tcl & Perl).
• Confident problem solver who thrives under pressure to find new, creative solutions.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
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