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Form of workJob Details:
Job Description:
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross functional teams to ensure design-kit leadership for customer enablement of cutting-edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define issue scope, plan execution, and innovate competitive solutions to meets customer needs.
Responsibilities are the following but not limited to:
Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies. Defines methodologies for hardware development related to technology node and EDA tool enabling. Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes. Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance. Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation. Builds deep understanding of digital design, verification, structural and physical layout, full-chip integration, power and performance, clocking, and/or timing to enhance future TFM development. Collaborates with EDA vendors on defining and early testing of next generation design tools.
This is an entry level position and compensation will be given accordingly.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a MS degree with 6+ months of experience or a PhD degree with 1+ years of experience in Electrical Engineering, Computer Science or related fields.
6+ months of experience in the following:
- Parasitic extraction experience in Device/transistor physics, modeling and technology scaling.
- Synopsys StarRC/ Cadence- Quantus QRC/ Mentor-Siemens XRC for transistor level using ICV/Calibre/PVS.
- Simulation modeling with vendor simulators (example: Synopsys-HSPICE, Cadence-Spectre, etc.)
Preferred Qualifications:
6+ months of experience in the following:
- Analog, Custom Design Flow.
- One of the following: Extraction, Fill, Custom Layout, Model, Simulation, Physical Verification, Reliability, ESD, IR/EM, etc.
- Programming knowledge in SKILL, Tcl, Python, or Perl.
- EDA tools such as Cadence Virtuoso/Spectre, Synopsys Custom Compiler/Hspice.
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Texas, Austin
Additional Locations:
US, California, Santa Clara, US, Oregon, Hillsboro
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$106,231.00-$159,109.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross functional teams to ensure design-kit leadership for customer enablement of cutting-edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define issue scope, plan execution, and innovate competitive solutions to meets customer needs.
Responsibilities are the following but not limited to:
Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies. Defines methodologies for hardware development related to technology node and EDA tool enabling. Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes. Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance. Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation. Builds deep understanding of digital design, verification, structural and physical layout, full-chip integration, power and performance, clocking, and/or timing to enhance future TFM development. Collaborates with EDA vendors on defining and early testing of next generation design tools.
This is an entry level position and compensation will be given accordingly.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a MS degree with 6+ months of experience or a PhD degree with 1+ years of experience in Electrical Engineering, Computer Science or related fields.
6+ months of experience in the following:
- Parasitic extraction experience in Device/transistor physics, modeling and technology scaling.
- Synopsys StarRC/ Cadence- Quantus QRC/ Mentor-Siemens XRC for transistor level using ICV/Calibre/PVS.
- Simulation modeling with vendor simulators (example: Synopsys-HSPICE, Cadence-Spectre, etc.)
Preferred Qualifications:
6+ months of experience in the following:
- Analog, Custom Design Flow.
- One of the following: Extraction, Fill, Custom Layout, Model, Simulation, Physical Verification, Reliability, ESD, IR/EM, etc.
- Programming knowledge in SKILL, Tcl, Python, or Perl.
- EDA tools such as Cadence Virtuoso/Spectre, Synopsys Custom Compiler/Hspice.
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Texas, Austin
Additional Locations:
US, California, Santa Clara, US, Oregon, Hillsboro
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$106,231.00-$159,109.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
