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Form of workLab Overview
The Samsung SOC Lab vision provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung's strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products.
Position Summary:
We are looking for a Lead SoC and System Power Modeling Architect to build a team and execute analysis and modelling of new SoC architectures and features for next generation mobile products. This SOC segment role will be a hands-on leader focused on guiding team approach to SOC Power Modeling, Power Simulation, Use Case Analysis and implement the future of SOC power optimization. This role will architect, optimize and deliver leading SoCs upon the Galaxy platform powering smartphones, tablets, wearables and technology beyond.
Position Responsibilities:
- Build a team of architects while guiding on development of grounds up power models for SoC to help optimize performance per area per power on various targeted workloads in next generation SoCs.
- Deliver power models for SoCs in new and existing markets.
- Evaluate power trade offs for architecture proposal in collaboration with team of SoC Architects and communicate the results across related engineering audiences (SW, HW, Architecture, Leadership).
- Perform power aware modeling, simulation and analysis of SoCs features for specified applications, benchmarks, and complex uses cases.
- Direct and orchestrate power modeling and studies to support inclusion of SoC features in the next generation SoC architecture based on performance, area or power improvement.
- Deliver power management architecture, microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership.
- Collaborate with silicon bring-up and product teams to verify and debug the power related issues and its delivered performance.
- Collaborate across teams to bring power management features and proposals to fruition across the SOC, Driver, OS, System through detailed documentations.
Required Skills:
- BSc, Masters or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience.
- 15+ years of experience in SOC or ASIC design and architecture.
- Prior direct experience (> 7 years) in Power modeling, Power architecture or power microarchitecture is required.
- High proficiency in power analysis and performance modeling, ranging from simple analytical models to complex cycle accurate performance model and correlation.
- Ability to leverage existing simulation capabilities [GEM5, FastSIM, Platform Architect] or create new simulation capabilities when necessary.
- Detailed knowledge of SoC Architecture, power modeling and analysis tools.
- Leadership across hardware, software, and platform groups to align all parties to a common vision.
