Analog Design Engineering Manager

Job Details:
Job Description:
Role and Responsibilities:

• Directs, guides, and manages the activities and performance of analog circuit design engineers for analog and mixed-signal IP/SoCs for group of junior engineers.
• Provides guidance on creating design drawings, test plans, electrical and timing analysis, evaluating components, interconnects used in integrated circuitry, and optimizing floorplans for power, performance, area, timing, and yield goals.
• Assesses, monitors, and mitigates operational risk in circuit engineering projects, reviews the documentation produced by the team, and monitors project budget, headcount, KPIs, and deliverables.
• Drives innovation in integrated circuitry design, design techniques, quality, and efficiency, and recommends cost saving opportunities relevant to circuit Design Engineering.
• Works collaboratively with RTL designers, physical designers, and verification engineers to improve upon areas of design inefficiencies.
• Collaborates cross functionally to report design progress and collect, track, and resolve any performance and circuit design issues pre and post-silicon.
• Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.
• Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.

Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
The candidate must possess a Bachelor's degree in Electrical Engineering, Computer Engineering or similar discipline with 7+ years of experience -OR- a Masters degree in Electrical Engineering, Computer Engineering or similar discipline with 5+ years of experience -OR- a PhD degree in Electrical Engineering, Computer Engineering or similar discipline with 3+ years of work experience.
Candidate should also possess:

• Strong understanding of VLSI Analog circuit design tradeoffs, small signal analysis, digital design and building blocks (flops, latches, sizing, Boolean algebra).
• Knowledge of design tools and flows such as Synopsys, Cadence.

Preferred Qualifications:

• Knowledge of highspeed IO signaling, transmission line theory, power delivery power and signal integrity and power integrity concepts, PLL, Noise analysis, Jitter, clocking, ADC, DAC, Switched-Cap circuits.
• Memory IO training, Firmware, IO link training algorithms, Micro-architecture specification documentation.
• Reliability experience: RV, ESD, Aging, Electrical overstress, Cross discipline knowledge in any of these areas: Analog integration, RTL, System Verilog, Static timing analysis, APR, Floor planning, Metal routing, PowerGrid.
• Software: Matlab, Scripting.
• Post-Si knowledge: Si characterization, Lab equipment (Oscilloscopes, BERT, VNA, signal generators).

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, California, Folsom, US, Massachusetts, Hudson
Business group:
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$162,041.00-$259,425.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.