Address
Form of workJob Details:
Job Description:
About Advanced Design:
Advanced Design Group under Design Enablement in Technology Development has primary focus of Design-Technology Co-optimization (DTCO) and Foundational IP development to support both the Technology Development organization and Intel's IP/Product design teams. Advanced power, performance, and area (PPA) analyses are conducted across domains to guide Technology Development's research, pathfinding, and technology definition.
Library Technology Group Standard Cell development team in Advanced Design is looking for a highly motivated individual to be part of pathfinding, development, and optimization of Standard Cell libraries to enable best-in-class IP and product design on all generations of Intel technology.
The successful candidate will be part of the advance design library team responsible for Standard Cells circuit design and optimization, physical design, design rules analysis and optimization, benchmarking and testchip library development.
About the Role and Responsibilities
The successful candidate will participate in design, development, and delivery of Standard Cell libraries using world-leading process technology for use by Intel's testchips and benchmarking design teams.
Responsibilities include, but are not limited to:
-Design and implementation of combinatorial and sequential circuits based on Intel's process technologies.
- Circuit extraction and optimization for power/performance/area/robustness
- Library characterization build, validation, release, supporting development and delivery for various process and PDK (process design kits) test-chips and benchmarking Standard Cells content.
- Std cells physical design, development and pathfinding activities including developing checkers and validation of it towards production capability.
Candidate must possess the following behavioral traits/skills:
- Written and verbal communication skills.
- Customer orientation, and ability to work with external and internal partners in a flexible manner are expected.
This is an entry level position and compensation will be given accordingly.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a MS degree with 6+ months of experience in electrical or computer engineering or related field.
- Experience using industry-standard design automation tools for one or more of the following areas: circuit simulation, cell characterization, physical design verification, and APR collaterals generation and validation.
Preferred Qualifications:
- Experience in digital circuit design, including CMOS combinatorial logic and sequential element design and layout.
- Advance process std cells design.
- Linux environment and its development tools.
- Scripting development (TCL, Perl, Python) or willing to learn new skills.
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Folsom, US, California, Santa Clara
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$91,500.00-$137,436.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
About Advanced Design:
Advanced Design Group under Design Enablement in Technology Development has primary focus of Design-Technology Co-optimization (DTCO) and Foundational IP development to support both the Technology Development organization and Intel's IP/Product design teams. Advanced power, performance, and area (PPA) analyses are conducted across domains to guide Technology Development's research, pathfinding, and technology definition.
Library Technology Group Standard Cell development team in Advanced Design is looking for a highly motivated individual to be part of pathfinding, development, and optimization of Standard Cell libraries to enable best-in-class IP and product design on all generations of Intel technology.
The successful candidate will be part of the advance design library team responsible for Standard Cells circuit design and optimization, physical design, design rules analysis and optimization, benchmarking and testchip library development.
About the Role and Responsibilities
The successful candidate will participate in design, development, and delivery of Standard Cell libraries using world-leading process technology for use by Intel's testchips and benchmarking design teams.
Responsibilities include, but are not limited to:
-Design and implementation of combinatorial and sequential circuits based on Intel's process technologies.
- Circuit extraction and optimization for power/performance/area/robustness
- Library characterization build, validation, release, supporting development and delivery for various process and PDK (process design kits) test-chips and benchmarking Standard Cells content.
- Std cells physical design, development and pathfinding activities including developing checkers and validation of it towards production capability.
Candidate must possess the following behavioral traits/skills:
- Written and verbal communication skills.
- Customer orientation, and ability to work with external and internal partners in a flexible manner are expected.
This is an entry level position and compensation will be given accordingly.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a MS degree with 6+ months of experience in electrical or computer engineering or related field.
- Experience using industry-standard design automation tools for one or more of the following areas: circuit simulation, cell characterization, physical design verification, and APR collaterals generation and validation.
Preferred Qualifications:
- Experience in digital circuit design, including CMOS combinatorial logic and sequential element design and layout.
- Advance process std cells design.
- Linux environment and its development tools.
- Scripting development (TCL, Perl, Python) or willing to learn new skills.
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Folsom, US, California, Santa Clara
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$91,500.00-$137,436.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
