Address
Form of workJob Details:
Job Description:
Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!
The selected candidate for the Physical Design Methodology Engineer will be responsible for but not limited to:
The ideal candidate should exhibit the following behavioral traits:
Ability to influence others and drive buy-in across organizational boundaries.
Qualifications:
What we need to see (Minimum Qualifications):
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
How to Stand out (Preferred Qualifications):
Amazing Benefits!
Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel's benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$119,130.00-$178,690.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!
- Life at Intel
- Diversity at Intel
The selected candidate for the Physical Design Methodology Engineer will be responsible for but not limited to:
- Define hard-IP integration specification requirements to support effortless IP-SoC integration and maximize IP reuse across projects on a given technology node.
- Lead global IP integration spec work-groups with representatives from DE, TFM enablement, SOC and IP design teams to drive consensus and ratify requirements.
- Collaborate on implementation and validation of IP signoff checks. You will own publication and maintenance of the HIP integration specification document.
- Coordinate and manage change requests to the POR HIP signoff requirements across all projects.
The ideal candidate should exhibit the following behavioral traits:
- Highly collaborative such to effectively drive stakeholder to winning results for Intel.
- Self-disciplined, motivated and innovative, with the ability to manage tasks of broad scope and complexity across organizational boundaries. The candidate manages and prioritizes requests across multiple projects, IP/product teams and stakeholders.
- Ability to excel in leading in a highly matrixed development environment.
Ability to influence others and drive buy-in across organizational boundaries.
Qualifications:
What we need to see (Minimum Qualifications):
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Bachelor's degree in electrical or computer engineering with at least 4 years' experience OR MS degree in Electrical or Computer Engineering with at least 3+ years additional experience, OR a PhD in Electrical or Computer Engineering with 1+ years additional experience, in Electrical Engineering or Physics, or related field.
- 2+ years' experience interfacing with process, design and design automation teams.
- 2+ years' experience of industry standard CAD tools/flows for digital and/or analog design. Specific experience with Cadence Virtuoso and Spectre/Hspice is a plus.
How to Stand out (Preferred Qualifications):
- 2+ years' experience leading edge process technologies, devices and the interactions with circuit design.
- 1+ years' experience with SoC integration challenges, IP collateral delivery and IP integration (at least one complete design cycle from RTL to tape in for a design partition or test chip).
Amazing Benefits!
Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel's benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$119,130.00-$178,690.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
