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Form of workSr. Engineer, ASIC Design
Summary:
The ASIC Engineer is responsible for design and integration of complex SoCs with both high-speed custom and digital blocks. You will work in a dynamic environment as part of a small IC design team, covering roles from custom circuit design to optical device design. Each team member is expected to contribute across a broad range of tasks and to gain new skill sets to grow with the company. The ideal candidate is a hands-on self-starter who can craft specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.
Essential Functions:
- Develop and optimize RTL designs for use in complex digital systems
- Develop verification methodology and test benches for digital and mixed-signal blocks
- Design and contribute to design for test (DFT) methodologies
- Contribute to automated design methodologies for ASIC physical design
- Work with designers to integrate custom blocks into a digital tool flow
Basic Qualifications:
- BS or MS in Electrical Engineering, Computer Engineering, or related fields
- 2 to 5 years of work or academic experience in ASIC design
- History of assuming responsibility for a variety of technical tasks and completing projects independently
- Proficient in Verilog for both RTL design and verification
- Proficient in ASIC synthesis (Genus, Design Compiler) and verification (XCelium, VCS, Questa) tools
- Proficient in scripting or programming languages
Preferred Qualifications:
- Experience designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.
- Proficient in writing timing constraints and deep understanding of timing analysis
- Experience with place-and-route (Innovus, ICC) and sign-off (Calibre DRC, LVS) tools
- Experience working on digital designs with multiple clock domains and clock dividers
- Working knowledge integrating custom blocks in a digital-top flow (LEF, lib, etc.)
- Working knowledge of the Cadence Virtuoso design environment for manual schematic entry, layout, and simulation
- Performed silicon bring-up, debug, and evaluation
- Programming experience in Python
- Knowledge of high-speed SerDes or SerDes components
Pay Range is $120K to $165K
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and please don't contact our managers or employees.
About Ayar Labs:
At Ayar Labs we’re about to revolutionize computing by moving data with light. We’re unleashing processing power for artificial intelligence, high performance computing, cloud and telecommunications by removing the bottlenecks created by today’s electrical I/O -- making it possible to continue scaling computing system performance. Ayar Labs is the first to deliver an optical I/O solution that combines in-package optical I/O chiplets and multi-wavelength remote light sources to replace traditional electrical I/O. This silicon photonics-based I/O solution enables chips to communicate with each other from millimeters to kilometers, to deliver orders of magnitude improvements in latency, bandwidth density, and power consumption.
With our strong collaborations with industry leaders and government, our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with renowned experts on challenging, paradigm-shifting work.
We are passionate about delivering in-package optical I/O at scale, leveraging the strength of our patent portfolio and our team of leading interdisciplinary experts. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to drive innovation and achieve big wins. Join our team and experience the possibilities.
Resources:
With our strong collaborations with industry leaders and government, our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with renowned experts on challenging, paradigm-shifting work.
We are passionate about delivering in-package optical I/O at scale, leveraging the strength of our patent portfolio and our team of leading interdisciplinary experts. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to drive innovation and achieve big wins. Join our team and experience the possibilities.
Resources:
- Executives from Intel and GLOBALFOUNDRIES share their thoughts on Ayar Labs and the promise of in-package optical I/O (video)
- Ayar Labs in the News and Recent announcements
- LinkedIn and Twitter
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, national origin, race, ethnicity, creed, gender, disability, veteran status, or any other characteristic protected by law.
