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SR. ENGINEER, ASIC DESIGN
Develop and optimize RTL designs for use in complex digital systems. Develop verification methodology and test benches for digital and mixed-signal blocks. Design and contribute to design for test (DFT) methodologies. Contribute t...
| Company | Ayar Labs |
|---|---|
| Address | San Jose, CA |
| Category | Engineering/Architecture/scientific |
| Job type | Full-Time |
| Date Posted | a month ago See detail |
Sr. Engineer, ASIC Design
Ayar Labs
San Jose, CA
Develop and optimize RTL designs for use in complex digital systems. Develop verification methodology and test benches for digital and mixed-signal blocks. Design and contribute to design for test (DFT) methodologies. Contribute t...
a month ago seen See more...
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