Company

Florida State UniversitySee more

addressAddressSalt Lake City, UT
type Form of workFull-Time
CategoryInformation Technology

Job description

Description:

Job Title: FPGA Design Engineer

Job ID: CS20231104-99519

Job Location: Salt Lake City, UT

Job Description:

We are looking for a talented FPGA design engineer with industry experience in wireless digital communications, modems, networking, and/or digital signal processing (DSP). We design advanced wireless digital communication systems and electronic warfare systems. Development efforts include the whole lifecycle of designs from proposals, requirement definition, coding, simulation, synthesis, place and route, verification testing, and system support. We are looking for an engineer who enjoys challenging work with a team of talented engineers and can work well both with a team and as an individual contributor. Salt Lake City provides incredible year-round outdoor recreation options and cultural experiences, and L3Harris values your work/life balance so you can enjoy these opportunities.

Areas of desired technical experience or education include:

  • Modulation
  • Demodulation
  • Digital filters
  • Forward Error Correction (FEC)
  • Electronic Warfare
  • Networking
  • Industry standard interfaces (e.g. 10/100/1000 Ethernet, SPI, UART, SDRAM, DDR3, JESD, PCIe, Ethernet).
  • FPGA verification through simulation and unit testing.

Qualifications:

  • Bachelor’s Degree and minimum 4 years of prior relevant experience or a Graduate Degree and a minimum of 2 years of prior related experience.

Preferred Skills:

  • Experience in either VHDL (preferred) or Verilog development languages.
  • Experience implementing complex modem and/or DSP circuits in programmable logic using FPGA devices. Equivalent experience in ASIC design is also applicable.
  • Experience in simulation, synthesis, and placement software tools such as ModelSim, Synplicity, Xilinx Vivado / ISE and/or Altera Quartus development tool sets.
  • Experience with HLS (High-Level Synthesis)
  • Experience with timing closure in large FPGAs.
  • Experience in laboratory debug techniques using digital scopes, logic analyzers, BERTS, and other complex measurement devices.
  • FPGA Design using High-speed serial interfaces (3+ Gbps)
  • Familiarity with a code revision management tool such as Git.
  • Familiarity with C/C++/C# and Matlab/Simulink.

Employment Type: Full Time
Refer code: 7552519. Florida State University - The previous day - 2024-01-01 20:01

Florida State University

Salt Lake City, UT
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