Company

Celestial AISee more

addressAddressSanta Clara, CA
type Form of workFull-Time
CategoryInformation Technology

Job description

Job Description

Celestial AI is the creator of the Photonic Fabric optical interconnect technology platform. Photonic Fabric provides the foundational technology for optically scalable, disaggregated data centers, to unleash advancements in AI with sustainable and profitable business models. Celestial AI has assembled a highly experienced team of industry leaders who have a track record of building multiple successful technology businesses. The company recently closed a Series B financing to accelerate our growth, bringing total funding to over $160 million. Celestial AI serves an addressable market that is projected by Cowen & Company to exceed $200 billion in 2030.

Job Description:

In this position you will play a key role in contributing to the development of advanced mixed signal layout for low power, high-speed, SERDES, sensors, PLL and other macros to be used in numerous products from high performance data center SOCs to low power consumer SOCs.

You will join a highly collaborative team, and your success will have a significant impact on our products 

ESSENTIAL DUTIES AND RESPONSIBILITIES:

  • Layout design of advanced SERDES and other analog and mixed signal macros in deep nanometer- level Fin-FET technologies
  • Tasks include planning and implementing block-level floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout
  • DRC, LVS and other physical verification tools
  • Participate in post-layout circuit performance analysis
  • Perform physical layout for custom structures in state-of-the-art nanometer-level CMOS technologies using Cadence tools.
  • Assist in taking part in floor planning, custom layout and verifying against design rules and schematics. 
  • Learn and ramp on new tools and methodologies
  • Develop realistic schedule for block-level layout including complete verifications

QUALIFICATIONS:

  • At least 10 years of hands-on Layout Design experience
  • Experience in layout of high-speed SerDes blocks and PLLs in advanced Fin-FET process
  • Good understanding of clock routing and shielding
  • Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating
  • Excellent team player

Location: This role can be based out of Santa Clara, CA, Orange County, CA or Toronto, Ontario, Canada

For California location:

As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $135,000.00 - $155,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.

We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.

Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.

#LI-Onsite

Refer code: 6634750. Celestial AI - The previous day - 2023-12-03 04:25

Celestial AI

Santa Clara, CA
Popular Layout Design Engineer jobs in top cities
Jobs feed

CLINICAL SUPERVISOR EMERGENCY ROOM (FT VARIED) - Now Hiring

The Valley Health System

Las Vegas, NV

Business Manager

Wellness Health Careers

Vancouver, WA

Retail Fulfillment Associate, Bozeman Gallatin Valley - Part Time - Now Hiring

Macys

Bozeman, MT

$16.50 - $20.35 per hour

Engineering / Information System Security Officer (ISSO)

Resource Management Concepts, Inc.

Quantico, VA

Sales Manager

Markey's

Des Moines, IA

CE Technician

Pegasus Building Services

San Diego, CA

Senior Principal Penetration Tester

Oracle

United States

Python Developer

Bcforward

Hoboken, NJ

Principal, Customer Strategy

League Inc.

Remote - Oregon, United States

IT Security Engineer III

Mitsubishi Heavy Industries

Houston, TX

Share jobs with friends

Related jobs

Senior Layout Design Engineer

Senior Mask Layout Design Engineer

Nvidia Corporation

Santa Clara, CA

a month ago - seen

Analog Layout Design Engineer

Intel

$83,077 - $124,371 a year

Santa Clara, CA

2 months ago - seen

Senior Engineer, Advanced Packaging Silicon Layout Design Engineer

Samsung Semiconductor

San Jose, CA

3 months ago - seen

ASIC Layout Designer Engineer (Contractor)

Samsung Semiconductor

San Jose, CA

4 months ago - seen

Analog Layout Design Engineer

Intel Corporation

Folsom, CA

4 months ago - seen

PCB Layout Design Engineer

Eurofins

Santa Clara, CA

5 months ago - seen

ASIC/Layout Design Engineer

Teledyne FLIR LLC

Goleta, CA

5 months ago - seen

Staff Engineer, Layout Design

InnoPhase

San Jose, CA

5 months ago - seen

PCB Layout Design Engineer

Eurofins USA Material Sciences

Santa Clara, CA

5 months ago - seen

PCB Design Layout Engineer

Nvidia Corporation

Santa Clara, CA

5 months ago - seen