Address
Form of workJob Details:
Job Description:
The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful. The IP Engineering Group is looking for energetic and passionate senior Design leaders to work closely with established ASIC design team for advanced digital IO controller (like PCIe, UPI, CXL, IOMMU etc) IP implementation on cutting edge technology nodes.
Your responsibilities will include to oversee definition, architecture design, and documentation for SoC development. Work on micro-architecture design, Logic Design, and system simulation. You will perform all aspects of the SoC design flow from high-level design to synthesis, place and route, timing, and power to create a design database that is ready for SoC integration. Mentoring and coaching junior verification engineers. Leadership to manage stakeholders with end-to-end objectives in mind.
The candidate should have the ability to work effectively with both internal and external teams/stakeholders. Should possess strong problem solving/communication skills. Should be a very good team player.
Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate should possess a bachelor's degree in electrical, Electronics, Computer Engineering or Computer Science or any related field with 5+ years' experience -OR - a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 4+ years' experience -OR- PhD degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 1+ years' experience in:
VLSI design. Verification/validation tests.
Expertise in System Verilog/C++/OVM or UVM methodology and/or Formal Verification techniques.
Preferred qualification:
System simulation models, and debugging RTL/tests.High speed serial links IPs (PCIe, UPI, CXL, IOMMU etc).Experience in Computer architecture and PCIe, UPI, CXL, IOMMU, Cache Coherency protocols
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$119,130.00-$178,690.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful. The IP Engineering Group is looking for energetic and passionate senior Design leaders to work closely with established ASIC design team for advanced digital IO controller (like PCIe, UPI, CXL, IOMMU etc) IP implementation on cutting edge technology nodes.
Your responsibilities will include to oversee definition, architecture design, and documentation for SoC development. Work on micro-architecture design, Logic Design, and system simulation. You will perform all aspects of the SoC design flow from high-level design to synthesis, place and route, timing, and power to create a design database that is ready for SoC integration. Mentoring and coaching junior verification engineers. Leadership to manage stakeholders with end-to-end objectives in mind.
The candidate should have the ability to work effectively with both internal and external teams/stakeholders. Should possess strong problem solving/communication skills. Should be a very good team player.
Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate should possess a bachelor's degree in electrical, Electronics, Computer Engineering or Computer Science or any related field with 5+ years' experience -OR - a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 4+ years' experience -OR- PhD degree in Electrical, Electronics, Computer Engineering or Computer Science or any related field with 1+ years' experience in:
VLSI design. Verification/validation tests.
Expertise in System Verilog/C++/OVM or UVM methodology and/or Formal Verification techniques.
Preferred qualification:
System simulation models, and debugging RTL/tests.High speed serial links IPs (PCIe, UPI, CXL, IOMMU etc).Experience in Computer architecture and PCIe, UPI, CXL, IOMMU, Cache Coherency protocols
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$119,130.00-$178,690.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
