Address
Form of workJob Details:
Job Description:
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure design-kits leadership for customer enablement for cutting edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define the scope, plan execution, innovate competitive solutions to meet customer needs.
The Engineering Manager position within the Design Enablement (DE) organization of Technology Development (TD) is chartered as an Applications and Support Manager position chartered to lead a team that drives customer solutions for ASIC tools/flows and Physical verification/runsets when customers use Intel PDK collaterals in these domains. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams (internal to Intel and external) to deliver quality solutions.
As a manager, set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance. Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost.
Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions. Provides guidance on employee development, performance, and productivity issues. Plans and schedules daily tasks, uses judgement on a variety of problems requiring deviation from standard practices. Inadequacies and erroneous decisions would cause moderate inconvenience and expense.
Candidate must exhibit the following behavioral traits/skills:
- Drive a customer-oriented culture in the team and provide with fast response times to user issues and concerns.
- Demonstrate experience in analytical problem-solving capability and teamwork with ability to work across organizational boundaries.
- Proven leadership skills, influencing skills and communication skills.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 9+ years of experience or MS degree with 6+ years of experience or PhD degree with 4+ years of experience in Electrical Engineer or Computer Engineering or related field.
5+ years of experience in two or more of the following:
- Technical management experience managing medium sized teams.
- Leading software development project and teams.
- Intel and/or external foundry process technology knowledge in advance nodes
- Industry direct experience to support customers in Asic/Physical Design and/or Physical Verification/runsets, in terms of technology, or EDA tools.
- In-depth knowledge on one of the domains; Physical Design or Physical Verification with breadth or familiarity on adjacent areas, for advanced technologies and be experienced in automation of workflows and manual tasks to improve quality.
- Ability to understand the technology challenges, and process changes that impact the Physical Design, Physical Verification and other PDK components.
Preferred Qualifications:
5+ years of experience in using industry standard software engineering principles and demonstrate ability to drive changes towards industry standard practices and methodologies.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$177,239.00-$283,471.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure design-kits leadership for customer enablement for cutting edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define the scope, plan execution, innovate competitive solutions to meet customer needs.
The Engineering Manager position within the Design Enablement (DE) organization of Technology Development (TD) is chartered as an Applications and Support Manager position chartered to lead a team that drives customer solutions for ASIC tools/flows and Physical verification/runsets when customers use Intel PDK collaterals in these domains. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams (internal to Intel and external) to deliver quality solutions.
As a manager, set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance. Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost.
Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions. Provides guidance on employee development, performance, and productivity issues. Plans and schedules daily tasks, uses judgement on a variety of problems requiring deviation from standard practices. Inadequacies and erroneous decisions would cause moderate inconvenience and expense.
Candidate must exhibit the following behavioral traits/skills:
- Drive a customer-oriented culture in the team and provide with fast response times to user issues and concerns.
- Demonstrate experience in analytical problem-solving capability and teamwork with ability to work across organizational boundaries.
- Proven leadership skills, influencing skills and communication skills.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 9+ years of experience or MS degree with 6+ years of experience or PhD degree with 4+ years of experience in Electrical Engineer or Computer Engineering or related field.
5+ years of experience in two or more of the following:
- Technical management experience managing medium sized teams.
- Leading software development project and teams.
- Intel and/or external foundry process technology knowledge in advance nodes
- Industry direct experience to support customers in Asic/Physical Design and/or Physical Verification/runsets, in terms of technology, or EDA tools.
- In-depth knowledge on one of the domains; Physical Design or Physical Verification with breadth or familiarity on adjacent areas, for advanced technologies and be experienced in automation of workflows and manual tasks to improve quality.
- Ability to understand the technology challenges, and process changes that impact the Physical Design, Physical Verification and other PDK components.
Preferred Qualifications:
5+ years of experience in using industry standard software engineering principles and demonstrate ability to drive changes towards industry standard practices and methodologies.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$177,239.00-$283,471.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
