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Form of workJob Details:
Job Description:
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross functional teams to ensure design-kit leadership for customer enablement of cutting-edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define issue scope, plan execution, and innovate competitive solutions to meets customer needs.
Responsibilities for this Design Silicon / CAD Intern role will be quite diverse in a technical nature. Experience and education requirements will vary significantly depending on unique needs of the job.
Job assignments are usually for the summer or for short periods during breaks from school.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications
Candidate must be pursuing a Master's or PhD degree in Computer Sciences, Electrical Engineering, or a related technical STEM degree.
Including:
- Software programming/software engineering at advanced undergraduate level or higher in procedural and/or object-oriented languages such as Python, C, Java, Lisp, or Pascal.
- College-level physics or electrical engineering with exposure to electronic circuit design.
- Demonstrated ability to use revision-control software such as git, perforce, CVS.
Preferred Qualifications:
- 1+ year undergraduate-level circuits and signals.
- 1+ term undergraduate-level experience to digital design and boolean algebra.
- Knowledge or experience maintaining open-source software.
- Github background or experience.
- Silicon engineering (VLSI design) experience such as Verilog RTL, Cadence Virtuoso layout, hspice circuit simulation.
Job Type:
Student / Intern
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, California, Los Angeles
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$63,000.00-$166,000.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross functional teams to ensure design-kit leadership for customer enablement of cutting-edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define issue scope, plan execution, and innovate competitive solutions to meets customer needs.
Responsibilities for this Design Silicon / CAD Intern role will be quite diverse in a technical nature. Experience and education requirements will vary significantly depending on unique needs of the job.
Job assignments are usually for the summer or for short periods during breaks from school.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications
Candidate must be pursuing a Master's or PhD degree in Computer Sciences, Electrical Engineering, or a related technical STEM degree.
Including:
- Software programming/software engineering at advanced undergraduate level or higher in procedural and/or object-oriented languages such as Python, C, Java, Lisp, or Pascal.
- College-level physics or electrical engineering with exposure to electronic circuit design.
- Demonstrated ability to use revision-control software such as git, perforce, CVS.
Preferred Qualifications:
- 1+ year undergraduate-level circuits and signals.
- 1+ term undergraduate-level experience to digital design and boolean algebra.
- Knowledge or experience maintaining open-source software.
- Github background or experience.
- Silicon engineering (VLSI design) experience such as Verilog RTL, Cadence Virtuoso layout, hspice circuit simulation.
Job Type:
Student / Intern
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, California, Los Angeles
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$63,000.00-$166,000.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
