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Form of workJob Description
We have an outstanding career opportunity for a DFT Engineer to join a leading Company located in the Irvine, CA surrounding area.
Salary Range: $150,000 - $250,000
Responsibilities:
- DFT implementation on a next-generation SoC project communication systems
- Define & document DFT requirements/Specifications for IP/Block and Chip level
- Execute DFT Lint to identify scan DRC violations and resolution
- Top-level and hard macroblock level scan insertion with high EDT compression ratio (Hybrid LBIST, EDT IP/ATPG, LPCT EDT, AC scan verification with high speed PLL, MBIST, and IJTAG)
- Plan and Insert MBIST and memory repair (BISR) at RTL
- Generate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG tests
- ATPG pattern verification on pre/post-route gate-level netlist, including 0-delay and SDF
- Work with the backend team for the MBIST/Scan mode constraints generation, scan reorder, VCDs for IR drop analysis during DFT, ECO changes and formal verification (LEC), and timing closure
- Support test engineer for pattern generation, tester debug, and failure analysis
- Work with the Test Engineering team during Silicon bring-up and creating flow/scripts necessary for debugging/diagnosing compression LPC ATPG patterns (stuck-at/at speed), MBIST patterns on ATE for development and production programs
- Expert knowledge of Mentor Tessent toolchain
Basic Hiring Criteria:
- Minimum 7 years of proven DFT execution experience on mixed-signal SoC with first-pass silicon success; 10 years of experience is ideal
- Hands-on hierarchical DFT flow experience from RTL to Netlist
- Strong knowledge and experience with both JTAG (IEEE1149.1) and IJTAG (1687)
- Experience in inserting EDT, wrapper cells, and OCC
- Experience in analyzing DFT DRC violations and fault coverage analysis
- Expertise in ATPG Debug and resolve ATPG DRC and chain trace issues
- Gate level simulations and debug; both 0-delay and with SDF DFT
- Expertise in using Cadence for scan stitching and Mentor Tessent tool suite for DFT implementation
- Experience in debugging tester/ATE failures, silicon bring-up, and yield and test time improvement
- Experience in Perl/TCL scripting and good verbal/written communication skills
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
TAD PGS, Inc. is a Global Fortune 500 company with worldwide revenue of over $27 billion and more than 50 years of government contracting experience. We specialize in supporting U.S. Government Agencies and their prime vendors by delivering a full range of recruitment and workforce solutions. As part of the Adecco family, we have access to over 2.5 million active candidates supporting hundreds of locations across North America. On any given day, we have more than 70,000 professionals working at client sites across the United States.
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
The Company will consider qualified applicants with arrest and conviction records.
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/
