Company

HardwareSee more

addressAddressAustin, TX
CategoryInformation Technology

Job description

As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple’s silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your experience and insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple’s DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems. CORE RESPONSIBILITIES: - Interacting with DV team to help solve their problems. Understand their problems and propose solutions to solve them. - Implement new functionality to solve emerging problems or to optimize already existing methods. - Drive high complexity development tasks, testing the solution and deployment to engineering teams - Leverage existing solutions, custom and industry-standard, and applying to solving problem at hand - Role involves debugging vendor tool problems.

Request

  • Familiarity with Verilog and SystemVerilog is a plus.
  • Familiarity with Xcelium or Modelsim or Synopsys VCS is required.
  • Strong communications skills and prior customer support experience is required.
  • Experience writing or maintaining the script or Makefile that builds the simulation program from RTL is a plus.
  • Familiarity with Verdi, Indago and/or SimView is a plus.
  • Scripting/coding abilities in Python/Perl is required.
  • Emulation experience on any available platforms, Palladium, Veloce or Zebu, including compilation, debug, performance and throughput tuning is a plus
  • Xilinx and Altera FPGA experience is a plus
  • Demonstrated experience with version control software (ie. Git, Perforce) and job schedulers (ie. LSF, NC) is required
  • Machine Learning experience is a plus
  • Deep knowledge of C/C++ or any other OOP programming language is required
  • Experience in Jaspergold (formal proofing, SEC, Reset Analysis) flows is a plus.
Refer code: 9170483. Hardware - The previous day - 2024-05-01 05:52

Hardware

Austin, TX
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