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Form of workJob Description/Responsibilities
At Achronix Semiconductor we develop FPGA-based hardware, software, and systems solutions to accelerate critical applications in areas such as 5G wireless infrastructure, network switching, and data center services. We work in small highly motivated teams of domain experts across the full product range, from high-level systems software to digital and analog circuit design, to create innovative products that are first-to-market and solve critical business needs.
You will have a unique opportunity to collaborate on a small team driving the development of a complete software and hardware stack for an FPGA-based Machine Learning inference accelerator card reference platform. You will adapt existing open-source and university software when possible, and develop new software from scratch as needed, to assemble a complete full-stack end-to-end software solution. This role works closely with sales and marketing, systems engineers, EDA tool developers, and FPGA architects. The resulting system will support diverse internal and external use models including FPGA fabric optimization, accelerator micro-architecture exploration, memory subsystem design, place & route software verification, system prototyping, pre-sales demonstrations, and customer deployment and scaling.
Prior experience is required working with an existing open-source or proprietary Machine Learning accelerator architecture such as OpenTPU, NVDLA, Eyeriss, or VTA. You must have a background in compiler hacking on one or more of TVM, Glow, Halide, Spatial, XLA, CLANG, LLVM, or GCC. Experience desired with compiler Intermediate Representations (IRs) and back-ends; JIT compilers; kernel-mode and user-mode Windows, Unix, or embedded systems runtime environments and device drivers. Familiarity is desired with Machine Learning frameworks such as TensorFlow, PyTorch, Caffe2, Keras and MXNet; domain-specific languages such as Halide and Spatial; and with common DNN models such as AlexNet, ResNet50, Inception, YOLO, RNN, and LSTM.
Skills:
Education:
MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, Applied Math, or Physics
At Achronix Semiconductor we develop FPGA-based hardware, software, and systems solutions to accelerate critical applications in areas such as 5G wireless infrastructure, network switching, and data center services. We work in small highly motivated teams of domain experts across the full product range, from high-level systems software to digital and analog circuit design, to create innovative products that are first-to-market and solve critical business needs.
You will have a unique opportunity to collaborate on a small team driving the development of a complete software and hardware stack for an FPGA-based Machine Learning inference accelerator card reference platform. You will adapt existing open-source and university software when possible, and develop new software from scratch as needed, to assemble a complete full-stack end-to-end software solution. This role works closely with sales and marketing, systems engineers, EDA tool developers, and FPGA architects. The resulting system will support diverse internal and external use models including FPGA fabric optimization, accelerator micro-architecture exploration, memory subsystem design, place & route software verification, system prototyping, pre-sales demonstrations, and customer deployment and scaling.
Prior experience is required working with an existing open-source or proprietary Machine Learning accelerator architecture such as OpenTPU, NVDLA, Eyeriss, or VTA. You must have a background in compiler hacking on one or more of TVM, Glow, Halide, Spatial, XLA, CLANG, LLVM, or GCC. Experience desired with compiler Intermediate Representations (IRs) and back-ends; JIT compilers; kernel-mode and user-mode Windows, Unix, or embedded systems runtime environments and device drivers. Familiarity is desired with Machine Learning frameworks such as TensorFlow, PyTorch, Caffe2, Keras and MXNet; domain-specific languages such as Halide and Spatial; and with common DNN models such as AlexNet, ResNet50, Inception, YOLO, RNN, and LSTM.
Skills:
- 2+ years of work or educational experience in machine leaning accelerator architectures, micro-architectures, and compilers.
- Skilled practitioner in C++, Python, and Verilog. Familiarity with System-C, System Verilog, HLS, Catapult-C, or Chisel.
- Experience in two of more of the following categories:
- Machine learning accelerators such as OpenTPU, NVDLA, Eyeriss, and VTA.
- Machine learning frameworks such as TensorFlow, PyTorch, Caffe2, Keras, and MXNet.
- Common DNN models such as AlexNet, ResNet50, Inception, YOLO, RNN, and LSTM.
- Domain-specific languages such as Halide and Spatial.
- Compilers such as TVM, Glow, Halide, CLANG, LLVM, and GCC.
- Embedded system runtime environments and device drivers
Education:
MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, Applied Math, or Physics
