Address
Form of workJob Details:
Job Description:
The Role:
The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of future technologies, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO (System Technology Co-Optimization). The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System.
Your responsibilities may include, but not be limited to:
- Establish 3DIC Test Cases across market segments for technology definition and test chip certification
- Development of 3DIC construction and validation methodology. Evaluation and feedback of 3D-IC TFM and EDA capabilities
- Design analysis and feedback for 3D silicon and packaging technologies development
- Collaboration with the different Product teams to identify critical product characteristics and target setting requirements.
- Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable product differentiation
The future of Moore's Law: 3D-IC
This is an entry level position and compensation will be given accordingly.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a PhD degree with 1+ years of experience in Electrical and Computer Engineering or related field.
1+ years of experience in the following:
- VLSI Design, Digital Design.
- Experience driving Physical Design place and route Synopsys/Cadence tools, design reference/sign-off flows in advanced technologies.
- Understanding of design methodology and tools features for IP/chip design.
- Scripting skills using a programming language such Python, TCL.
- Circuit design and silicon technology. Design challenges in advanced technologies.
Preferred qualifications:
2+ years of experience in the following:
- Computer Architecture.
- 3D-IC Silicon and packaging technologies.
- Machine Learning.
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$123,419.00-$185,123.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
The Role:
The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of future technologies, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO (System Technology Co-Optimization). The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System.
Your responsibilities may include, but not be limited to:
- Establish 3DIC Test Cases across market segments for technology definition and test chip certification
- Development of 3DIC construction and validation methodology. Evaluation and feedback of 3D-IC TFM and EDA capabilities
- Design analysis and feedback for 3D silicon and packaging technologies development
- Collaboration with the different Product teams to identify critical product characteristics and target setting requirements.
- Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable product differentiation
The future of Moore's Law: 3D-IC
- https://www.intel.com/content/www/us/en/newsroom/opinion/moore-law-now-and-in-the-future.html
- https://www.zdnet.com/paid-content/article/moores-law-under-the-microscope-intel-advances-transistor-technology/
- https://www.tomshardware.com/news/intel-teases-falcon-shores-xpu
This is an entry level position and compensation will be given accordingly.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a PhD degree with 1+ years of experience in Electrical and Computer Engineering or related field.
1+ years of experience in the following:
- VLSI Design, Digital Design.
- Experience driving Physical Design place and route Synopsys/Cadence tools, design reference/sign-off flows in advanced technologies.
- Understanding of design methodology and tools features for IP/chip design.
- Scripting skills using a programming language such Python, TCL.
- Circuit design and silicon technology. Design challenges in advanced technologies.
Preferred qualifications:
2+ years of experience in the following:
- Computer Architecture.
- 3D-IC Silicon and packaging technologies.
- Machine Learning.
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$123,419.00-$185,123.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
