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Form of workJob Description
About InnoPhase, Inc.
INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications. To learn more about InnoPhase, visit www.innophaseinc.com.
As a Senior Staff Engineer or above, you will be collaborating with a team of design engineers to develop novel SoC products for connectivity and communications. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. You will also support other discipline teams to bring the SoC device to successful mass production.
This position can be based in either San Diego, CA or San Jose, CA
Key Responsibilities
- Review and contribute to SoC system architecture and product specifications
- Technical leadership supporting team resource planning, project scheduling and tracking
- Perform all aspects of complex SoC design flow from micro-architecture definitions, CPU/bus/memory sub-system design, IP integration, and verification through physical implementation
- Work with IP/Design Verification/Firmware/Software System/Production teams to provide necessary support for timely closure of SoC design and implementation issues
Job Requirements
- MS/Ph.D. in EE or equivalent and 15 or more years of experience in SoC development and mass production
- Knowledge of ARM/RISC Architectures, Multi-core CPU operation and system memory partition/hierarchy
- Experience with AMBA AXI/AHB/APB Protocol bus architecture specification and implementation
- Thorough knowledge of Verilog/VHDL/System Verilog languages and front-end tools such as simulation, linting, clock-domain crossing checking, formal verification
- Proven knowledge of constraint definition, synthesis, static timing analysis and complete Front to Back SoC design/implementation flow
- Understanding of SCAN ATPG, BIST, DFT/DFM and fault coverage analysis
- Proven knowledge of System Verilog/UVM methodology and other advanced design verification techniques
- Proficiency of programming/scripting languages such as C/C++, Perl, Tcl, and Python
- Great collaborator and team player with effective communication/presentation skills and aggressive schedule/quality result driven mentality
