Digital Engineer Vhdl

Digital Engineer
Remote available after a few weeks on site.
9/80 schedule
US Citizenship (no clearance)
Could convert to direct hire if candidate proves out to be a fit
Description
Developing/Updating a UVM verification environment for formal verification of 6 FPGAs.
Linux machines. Identifying any gaps in the verification environment for covering requirements. Updating UVM verification environment with test cases for reaching 95% statement coverage.
Requirements
BSEE
5 years (10 desired) writing SystemVerilog and UVM as a primary job function
VHDL
Linux command line workflows
TCL to control verification tools
Root-cause analysis of test failures
Experience working closely with RTL designers to collaboratively resolve verification test failures
Git SCM using LFS and Submodules
Desired:
• Experience creating prediction models from functional requirements documentation using SystemVerilog or SystemC
• Experience with DPI based simulator interaction for stimulus and prediction
• Proficiency scripting in either Perl or Python for parsing and manipulating text files
• Experience with Questa Sim and Visualizer
• Experience with the UVM-Framework workflow
• Experience writing split Class/xRTL BFMs for use with both simulation and Co-Emulation (Veloce experience preferred)
• Experience writing and maintaining Verification Plan Documents
• Experience working on USG Contracts and the associated documentation/process expectations
• Experience with common interface specifications used in spacecraft
• Experience verifying designs targeting radiation hardened Virtex FPGAs