Design Verification Engineer

Key Responsibilities:

• Verifying the FPGA RTL for complex digital blocks.
• Writing the verification plan.
• Developing verification environments to support FPGA IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM according to the functional/code coverage goals.

Required Experience:

• System Verilog and VHDL.
• UVM expertise. Able to Create UVM agents and other UVM components such as prediction models (without any templates or frameworks).
• Requirement based verification.

Preferred Experience:

• DO-254.
• Component-level verification: the candidate would be working on block levels.
• Requirements management tool, such as Doors.
• Ethernet and AXI-Lite/AXI protocols.
• Xilinx/Microsemi FPGA knowledge.
• Synopsys verification EDA tools

Job Type: Contract

Pay: $55.22 - $65.80 per hour

Expected hours: 40 per week

Benefits:

• Referral program

Schedule:

• 8 hour shift
• Day shift
• Monday to Friday
• No nights
• No weekends

Willingness to travel:

• 25% (Required)

Work Location: Remote