Design Verification Engineer

About us

We are searching for talented individuals who are driven to tackle the most ambitious goal of our time - building the computer hardware that enables the development of safe artificial general intelligence. See more at fathomradiant.co/aboutus

In our people, we above all value kindness, a scout mindset, a focus on improvement, and prioritising to get the right things done. We aim to help build one of the most transformative technologies in the world, with massive social and ethical implications. We think this makes representation even more important, and we are actively striving to have a range of diverse perspectives on our team.

This role

We are looking for a Design Verification lead with a strong background in ASIC verification an interest in communication networks. As the lead Design Verification Engineer you will work closely with other engineer teams to drive all aspects of the verification effort for our custom chip. Your primary scope of ownership will include verification planning, verification environment development, as well as leading both block-level and chip level functional verification effort for Fathom's ASIC designs.

This role is open to remote from anywhere in the world, but we have strong preference towards availability in US and / or Central Europe timezones.

This role aims for multiple hires in different seniority levels.

Areas of contribution

• Develop and maintain comprehensive verification plans that covers all aspects of the Design Verification to ensure design correctness of one or more of the following system components:
• RDMA / MPI Protocol Engine
• Transport / Forwarding Logic
• Shared-Memory Switch (min. 3.2Tbps performance)
• Ethernet Port Logic (Ethernet 802.3bj/ck/df/dj)
• Lead the development and implementation of verification environments, testbenches, and test cases using industry-standard verification methodologies, tools, and frameworks
• Work closely with the design team to understand and validate the design requirements and specifications and to debug and resolve any issues that arise during the verification process

Requirements (necessary skills for this role):

• M.S. or PhD degree in Computer Science, Electrical Engineering, or a related field, CS background preferred
• 3+ years of experience with directed and constrained-random functional verification and performance validation, particularly developing and maintaining verification test-benches, test cases, and test environments using UVM/SystemVerilog.
• Strong problem-solving and debugging skills.
• Excellent communication and collaboration skills.

Nice-to-haves (we will prioritize candidates that also have these skills):

• Demonstrated experience in the verification of at least one of the four system components listed in Areas of Contribution is highly desirable.
• Experience developing models and integrating Verilog with other simulators using C++ and Python.
• Experience scripting using Perl or shell scripts.
• Exposure to Formal Verification

$110,000 - $210,000 a year

The salary range is an estimation for US only and is applicable to a wide seniority level. Salary range for candidates out of the US will be determined based on the market salaries and living expenses of the specific country.

For all roles, we target market salaries, with an additional benefits package. Our comprehensive benefits include startup equity and medical expenses coverage (including extra coverage for employees with a family). The salary in our offers are determined based on years of experience, living expenses (for remote roles) and our internal salaries.