Job description
As a Senior RFIC-PLL Designer, you are going to be responsible for providing analog and digital PLL solutions for wireless SoC and driving them to mass production for Apple’s Wireless Connectivity products. Responsibilities include:- Lead design of radio transceiver chains including analog PLLs - VCOs, digital PLLs - DCOs, LOGen, and chain of blocks in RX and TX for wireless connectivity products. - Drive radio KPI (power, area, performance) to meet product requirements- Work with cross-functional teams including platform architecture, wireless design, RF HW and SW to define radio features enabling wireless innovation.- Work closely with RF Systems in block level and high level specifications of the PLL-LOGen, TX and RX line ups, and proper distribution of spec margins in the chain. - Hands-on design contributions starting from concept, architecture and topology to transistor-level feasibility studies and KPI trade-off analysis to actual design, simulations and extractions. - Design of RF and Analog loopbacks for calibration and compensation. - Work through Co-Existence scenarios and design to meet the CoEx requirements. - Oversee the floorplan layout and verification of the design to ensure a successful tape-out. - Close collaboration with RFIC test engineers in the bring up, debug and optimization of the wireless connectivity chip through the productization.- Provide design versus silicon measurements correlation, and compliance with specification for a volume production.
Address
Irvine, CA
