Job description
The successful candidate will: - Own RTL integration, assembly, partitioning, transformation and analysis. - Package, qualify and deliver FE design collateral. - Triage logic equivalence failures between designs. - Ensure implementation readiness with RTL lint, clock/reset/power domain crossing checks and unit level synthesis. - Develop innovative methods to improve front-end Design Integration process. - Author specifications for design units. - Review and signoff specifications for customers and IP providers. - Collaborate effectively with Architecture, IP, DV, SOC, DFT, Synthesis, P&R and STA teams spanning multiple sites.
Address
Santa Clara, CA
