Soc Power Management Micro-Architect

Job Details:
Job Description:
Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!
• Life at Intel
• Diversity at Intel
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.
If you are passionate about GPU for AI driven workload and working with leading graphics engineers on Intel's latest GPU/CPU architectures, then our Datacenter GFX and AI Engineering (DGAI) Team has opportunities for you. Datacenter GFX and AI Engineering (DGAI) is responsible for delivering industry-leading GPU hardware Intellectual Property (IP) blocks and system-on-chip (SoC) products for High Performance Computing (HPC). We strive to lead the industry through continuous innovation and world-class engineering. The Discrete Graphics SoC team is within DGAI and we are responsible to work with state of the art technologies and great Power Performance Area (PPA) architectures. As a member of Reset, Power Management and Clocking team, you will be working on low-power solutions for various aspects and design blocks along with SoC clocking. You will be collaborating with architects, RTL Validation, Platform and Software teams to analyze and implement low-power solutions, SoC clocking for next generation Intel GPU products for HPC. We work closely with partners across Intel and we are looking for a SoC Design Engineer to join our team.
The key responsibilities of this person include the following:

• Participate in the development of Architecture and Microarchitecture specifications for SOC Level Clocking, Reset and/or Power Management features
• Define and implement new features in RTL at IP or SOC level
• Collaborate with cross-functional teams (FW, Validation, SD, SV, etc.) to make sure designs are delivered on time and with highest quality
• Closely work with Verification team and help define test plan and debug design.
• Participate and drive timing convergence for high speed designs including micro-architecture optimizations.
• Experience with design tools and flows such as Lint, CDC/RDC, UPF/VCLP

The SoC Power Management Micro-Architect should possess the following attributes:

• Good communication and collaboration skills.
• Possess strong teamwork, problem-solving and influencing skills along with abilities to work with different geographical locations
• Ability to work independently and proactively to lead technical activities

Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
What we need to see (Minimum Qualifications):
Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science or related technical field with 9+ years' experience OR a Master's degree in in Computer Engineering, Electrical Engineering, Computer Science or related technical field with 6+ years' experience OR a PhD in Computer Engineering, Electrical Engineering, Computer Science or related technical field with 4+ years' experience.
Your experience should be in the following:

• Strong experience with Design of Data path Power management flows Arbitration logic , Clock Domain Crossing and State Machines.
• Experience in SoC Global Power Management.
• High performance digital logic designs and integration.
• SOC architecture, design flows and debug skills.
• RTL design using Verilog/System Verilog.

How to Stand out (Preferred Qualifications):

• Expertise with understanding of the power Management, reset, clock, and power domain challenges for large SoCs.
• Knowledge of low power design, tools and methodologies.
• Power intent UPF specifications knowledge a plus.
• Front-End/RTL tools and design methodologies.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
US, California, Santa Clara
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$162,041.00-$259,425.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.