Address
Form of workJob Details:
Job Description:
Become a member of one of the largest engineering companies in the world. Welcome to join an industry leading signaling development team at Intel Corporation. We are the enterprise platform Signal Integrity group within DPEA (Data Platform Engineering and Architecture Group).We are responsible for developing platform interconnect/interface solution for state-of-the-art server platforms, which support the latest Intel Xeon processors and other server products; You will work side by side with industry experts and leaders in memory Signal Integrity. You will also work to develop next generation technology. The work that we do today will be the backbone to the data centers and AI of tomorrow.
In this position, you will be working with a team of Signal Integrity Engineers. Your scope of responsibilities will include but are not limited to: Performing modeling and simulation of high-speed interface interconnects/channel. Working in lab to perform measurement, and correlating measurements to simulations. Working with silicon designers, platform designers, package designers, electrical validation teams, etc. to support interconnect and interface performance requirements. Contributing to package and platform design guideline development. Reviewing and evaluating package and board design and providing review feedback; Electrical modeling and simulation of high speed IO interconnects, such as PCIe and DDR. Development of package and platform design guidelines. Definition and evaluation of circuit design features required to support interconnect performance requirements. Creation of signal measurement test plans and review of measurement results. Correlation of measurements to simulations, and modification of models as required. Support Signal Integrity tool and methodology development.
Qualifications:
Minimum Requirements:
Applicants should possess a PhD in Electrical Engineering or a Master's Degree or a Bachelor's degree with at least 2 + years of experience or working knowledge in the following:
Preferred Requirements:
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Folsom
Business group:
The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies-spanning software, processors, storage, I/O, and networking solutions-that fuel cloud, communications, enterprise, and government data centers around the world.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$106,231.00-$159,109.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
Become a member of one of the largest engineering companies in the world. Welcome to join an industry leading signaling development team at Intel Corporation. We are the enterprise platform Signal Integrity group within DPEA (Data Platform Engineering and Architecture Group).We are responsible for developing platform interconnect/interface solution for state-of-the-art server platforms, which support the latest Intel Xeon processors and other server products; You will work side by side with industry experts and leaders in memory Signal Integrity. You will also work to develop next generation technology. The work that we do today will be the backbone to the data centers and AI of tomorrow.
In this position, you will be working with a team of Signal Integrity Engineers. Your scope of responsibilities will include but are not limited to: Performing modeling and simulation of high-speed interface interconnects/channel. Working in lab to perform measurement, and correlating measurements to simulations. Working with silicon designers, platform designers, package designers, electrical validation teams, etc. to support interconnect and interface performance requirements. Contributing to package and platform design guideline development. Reviewing and evaluating package and board design and providing review feedback; Electrical modeling and simulation of high speed IO interconnects, such as PCIe and DDR. Development of package and platform design guidelines. Definition and evaluation of circuit design features required to support interconnect performance requirements. Creation of signal measurement test plans and review of measurement results. Correlation of measurements to simulations, and modification of models as required. Support Signal Integrity tool and methodology development.
Qualifications:
Minimum Requirements:
Applicants should possess a PhD in Electrical Engineering or a Master's Degree or a Bachelor's degree with at least 2 + years of experience or working knowledge in the following:
- In-depth understanding of transmission line theory and electromagnetic field concepts.
- Design and analysis of high-speed digital interconnects, such as PCIE, DDR, ENET.
- Signal integrity simulation tools, such as HSpice, ADS.2D and 3D field solver tools, such as HFSS.
- Lab equipment, such as oscilloscopes, TDRs or VNAs.
Preferred Requirements:
- Experience with silicon device modeling methods, such as IBIS-AMI or Verilog-A.
- Experience in PCB layout review and associated tools, such as Cadence or Mentor.
- Experience using scripting languages, such as Matlab or Python.
- Experience in design of package, connector, cable, socket, etc.
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Folsom
Business group:
The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies-spanning software, processors, storage, I/O, and networking solutions-that fuel cloud, communications, enterprise, and government data centers around the world.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$106,231.00-$159,109.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
