Senior Verification & Emulation Engineer

Aeva's mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions. 

As a key member of the SoC Emulation & Validation development team, you will be responsible for developing bare metal driver firmware and validating key IPs in ARM-based SOCs for advanced perception applications using 4-D Lidar. 

What you'll be doing:

• Develop Emulation/Silicon Validation tests from SoC Verification tests
• Design and implement bare metal driver code (diagnostic firmware) using C to validate advanced ARM-based SOC
• Develop Firmware for pre-silicon and post-silicon validation of current and future SOCs.
• Validation on pre-silicon emulation, FPGA, and post-silicon validation platforms 
• Follow modular development practices so firmware is reusable across verification, validation, and mission firmware teams. 
• Implement, run, and debug validation tests for block, subsystem, and full chip. 
• Continuously enhance tools and methodologies used for validation.
• Work in a dynamic and fast-paced startup environment and with a team of passionate engineers 
• Work with Architects, design, verification, and mission firmware Teams to define system-level validation plans and prove that SOC meets the functional, coverage, performance, and power targets of the architecture and design. 

What you'll have:

• 8+ years of experience in hardware RTL/verification and validation 
• Experience in pre-silicon verification, emulation, FPGA, and post-silicon validation platforms 
• Hands-on experience developing bare metal firmware for IPs such as LPDDR, Ethernet, I2C, SPI, eMMC, Watchdog Timers, Interrupts, GPIOs, PLLs, UART, high-speed serdes etc.
• Proficient in debugging complex SOC or CPU core designs using industry-standard debugging tools - JTAG, Lauterbach, etc. 
• Proficient in C/C++, assembly, Perl/Python, and GIT. 

Nice to haves:

• Experience in SOC verification flow and methodology - using C/C++ and SV/UVM flow
• Experience in running simulations and debugging RTL and FW issues in simulation env

$154,900 - $209,600 a year

Salary pay ranges are determined by role, level, and location. Within the range, the successful candidate's starting base pay will be determined based on factors including job-related skills, experience, certifications, qualifications, relevant education or training, and market conditions. These ranges are subject to change in the future.