Runtime Software Engineer, Principal

Location
Santa Clara, Ca
Type
Full time
Department
R&D - Runtime Software
Compensation
IC6
$180K – $300K • Offers Equity • Offers Bonus
The pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.
d-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI compute has been to break through the memory wall to minimize data movements. We’ve achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chiplets and In-Memory compute approach. We are on track to deliver our first commercial product in 2024. We are poised to meet the energy and performance demands of these Large Language Models. The company has 100+ employees across Silicon Valley, Sydney and Bengaluru.

WHAT YOU WILL DO:

d-Matrix is developing an AI inference processor for accelerating the inference of NLP, Vision, and Recommendation workloads, in a data center environment. The architecture uses an in-memory compute processor subsystems, with a mix of fixed-point and floating-point data types in both dense and sparse matrix processing modes. During the seed round, the company has developed a 6nm CMOS test chip, and validated the architecture using real inference workloads compiled from PyTorch.
The position is a Runtime SW Engineer to work on the architecture and development, and validation of the functionality and efficiency of firmware/ software which is executed on System on Chip’s multiple processors, and low level drivers and system programs which hosts this System on Chip.
In this role, you will be largely responsible for all aspects of runtime performance of the silicon product. You will architect, document, and develop the runtime firmware that executes in the various on-chip multi-core CPU subsystems. This firmware will be controlling all aspects of the AI subsystems in the chip and will be architected to maximize the utilization of the hardware. Measures of success will be overall AI hardware utilization, minimizing communication bottlenecks and maximizing on-chip memory utilization.
You will bring the software up on FPGA platforms (that contain images of the embedded CPU subsystems) and debug it using JTAG-connected IDE. You will develop a firmware solution that can be developed and tested ahead of the availability of the AI subsystem hardware.
You will be responsible for determining the delivery schedule, and ensuring the software meets d-Matrix coding and methodology guidelines. You will collaborate with the hardware teams (to interpret the hardware specifications, and suggest changes that improve utilization and throughput, and-or reduce power). You will collaborate with other members of the SW team (located in AU and US), the SW quality & Test team (US and India), as well as the HW verification team (to assist with SoC-level DV simulations and emulation).
You will be developing and debugging code on the FPGA-based systems containing CPU subsystems and SystemC models of the AI subsystems and SoC You will also be involved in porting the software to a “big iron” emulation system (e.g. Veloce, Palladium) containing the final RTL.
You will also be closely involved in the bring up of the software on the AI subsystem hardware and validating silicon and software performance.