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Form of workJob Details:
Job Description:
In the Runset QA domain and as a DRC/LVS Physical Verification and QA Engineer, you are expected to perform the following:
- Develop test patterns to qualify design rules for correct implementations.
- Develop automation to run regressions, auto detect issues and generate validation reports.
- You are also expected to file bug reports and work closely with runset developers and rule writers on validating the rules.
- Work closely with Technology development on providing feedback on rule wording and correctness.
- Partner with rules owners to ensure clarity and accuracy of rules.
- Work with EDA on tool developments/improvements to enhance performance, add functionality and improve capacity.
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.
Your responsibilities will include, but are not limited to:
- Designs, develops, tests, and debugs software tools, flows, PDK design components, and/or and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing.
- Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end to end testing of the software tools.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 3+ years of experience or MS degree with 2+ years of experience or PhD degree with 1+ years of experience in electrical engineering, computer engineering, computer science or related fields.
Experiene in the following:
- Developing Calibre or ICV runsets and validation test cases.
- Design Rule Development using Calibre (SVRF and TVF), with exposure to VLSI design and execution.
- fluent in at least one of the following: TCL, Python, Unix-Linux platforms.
Preferred Qualifications:
Experience in the following:
- Developing test cases to validate DRC, LVS, antenna, density, and fill modules.
- Calibre PERC, and Cadence Pegasus.
- Layout and/or schematic entry using Cadence Virtuoso and/or Synopsys Custom Designer.
- Semiconductor device physics models and technology scaling.
-Algorithmic development and translating rules into runsets.
-Familiar with industry standard CAD tools flows for digital analog design
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$123,419.00-$185,123.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
In the Runset QA domain and as a DRC/LVS Physical Verification and QA Engineer, you are expected to perform the following:
- Develop test patterns to qualify design rules for correct implementations.
- Develop automation to run regressions, auto detect issues and generate validation reports.
- You are also expected to file bug reports and work closely with runset developers and rule writers on validating the rules.
- Work closely with Technology development on providing feedback on rule wording and correctness.
- Partner with rules owners to ensure clarity and accuracy of rules.
- Work with EDA on tool developments/improvements to enhance performance, add functionality and improve capacity.
At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.
Your responsibilities will include, but are not limited to:
- Designs, develops, tests, and debugs software tools, flows, PDK design components, and/or and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing.
- Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end to end testing of the software tools.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 3+ years of experience or MS degree with 2+ years of experience or PhD degree with 1+ years of experience in electrical engineering, computer engineering, computer science or related fields.
Experiene in the following:
- Developing Calibre or ICV runsets and validation test cases.
- Design Rule Development using Calibre (SVRF and TVF), with exposure to VLSI design and execution.
- fluent in at least one of the following: TCL, Python, Unix-Linux platforms.
Preferred Qualifications:
Experience in the following:
- Developing test cases to validate DRC, LVS, antenna, density, and fill modules.
- Calibre PERC, and Cadence Pegasus.
- Layout and/or schematic entry using Cadence Virtuoso and/or Synopsys Custom Designer.
- Semiconductor device physics models and technology scaling.
-Algorithmic development and translating rules into runsets.
-Familiar with industry standard CAD tools flows for digital analog design
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$123,419.00-$185,123.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
