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Form of workJob Details:
Job Description:
As a member of the Logic Design and Validation group within the Lead Vehicle Development group in Design Enablement you will be part of a team that develops the RTL models and pre-silicon validation tests for test chips on the next generation Intel silicon manufacturing process.
Your responsibilities would include:
- Creating new digital, analog, and mixed-signal RTL models for new and existing designs.
- Running the Functional Equivalence Verification (FEV) flow to compare RTL to schematics.
- Owning the creation of pre-silicon validation test plans, formal SystemVerilog/UVM testbenches, and validation test cases.
- Owning RTL design of new digital systems ranging from design-for-test (DFT) on existing systems to novel designs to enable Power-Performance-Area (PPA) studies on next-generation technology nodes.
The ideal candidate should exhibit the following behavioral traits:
- Motivated, driven, with sense of urgency and commitment to achieve targeted goals.
- Communication and problem-solving skills.
- Documentation, and presentation skills .
- Troubleshooting and analytical skills.
This is an entry level position and compensation will be given accordignly.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a BS degree with 3+ months of experience or MS degree with 6+ months of experience in Electrical Engineering, Computer Engineering, or related fields .
Experience above is the following:
- Digital design using Verilog or SystemVerilog.
- Performing Pre-Silicon Logic Validation at Unit level or Integration level.
- Experience with OVM/UVM test benches and verification concepts.
- Object Oriented Programing (OOP) in any programing language, preferably in SystemVerilog.
- SystemVerilog Assertions (SVA), their creation and application in closing validation coverage.
- Coverage-based verification and how to leverage for efficient validation closure.
Preferred Qualifications:
6+ months of experience in the following:
- Analog circuits and their interaction with digital systems.
- Experience in the Unified Power Format (UPF) specification.
- Scripting and automation with languages such as Perl or Python.
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
As a member of the Logic Design and Validation group within the Lead Vehicle Development group in Design Enablement you will be part of a team that develops the RTL models and pre-silicon validation tests for test chips on the next generation Intel silicon manufacturing process.
Your responsibilities would include:
- Creating new digital, analog, and mixed-signal RTL models for new and existing designs.
- Running the Functional Equivalence Verification (FEV) flow to compare RTL to schematics.
- Owning the creation of pre-silicon validation test plans, formal SystemVerilog/UVM testbenches, and validation test cases.
- Owning RTL design of new digital systems ranging from design-for-test (DFT) on existing systems to novel designs to enable Power-Performance-Area (PPA) studies on next-generation technology nodes.
The ideal candidate should exhibit the following behavioral traits:
- Motivated, driven, with sense of urgency and commitment to achieve targeted goals.
- Communication and problem-solving skills.
- Documentation, and presentation skills .
- Troubleshooting and analytical skills.
This is an entry level position and compensation will be given accordignly.
#DesignEnablement
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must possess a BS degree with 3+ months of experience or MS degree with 6+ months of experience in Electrical Engineering, Computer Engineering, or related fields .
Experience above is the following:
- Digital design using Verilog or SystemVerilog.
- Performing Pre-Silicon Logic Validation at Unit level or Integration level.
- Experience with OVM/UVM test benches and verification concepts.
- Object Oriented Programing (OOP) in any programing language, preferably in SystemVerilog.
- SystemVerilog Assertions (SVA), their creation and application in closing validation coverage.
- Coverage-based verification and how to leverage for efficient validation closure.
Preferred Qualifications:
6+ months of experience in the following:
- Analog circuits and their interaction with digital systems.
- Experience in the Unified Power Format (UPF) specification.
- Scripting and automation with languages such as Perl or Python.
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Business group:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
