DUTIES:
- Responsible for all aspects of physical implementation from RTL to GDS, including RTL synthesis, scan stitching, timing constraints creation, Power analysis, chip floor plan, clock distribution, full chip assembly, Timing driven Placement & Route, Static Timing Analysis, timing closure, ECO and tapeout.
REQUIREMENTS:
- Master of Science in Electrical, Electronics, or Computer Engineering or a closely related field. The position also requires knowledge of RTL design and the ability to use synthesis tools, placement route implementation tools, static timing analysis tools, logic equivalence checking tools, power grid analysis tools, and design rule checking tools.
Diversity drives innovation at Cirrus Logic. Different approaches, ideas and points of view are both valued and respected, and employees are rewarded for their skills, experience and performance. Additionally, Cirrus Logic is an Equal Opportunity/Affirmative Action Employer, and we do not discriminate on the basis of race, color, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, gender identity, genetic information or any other characteristic protected by law.