Phy Design Verification Engineer

- Verification experience of wireless/wired communication block/subsystem preferred.- Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.- Knowledge and experience of ASIC verification flows including test bench development, constrained random testing, and code/functional coverage.- Experience of using Matlab/C reference model and bit-accurate verification a plus.- Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.- Proficient in shell and Perl scripting, Python skills a plus.- Should be a team player with excellent communication skills, self-motivated, and well organized.