Memory DTCO Staff Engineer

Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!

• Life at Intel
• Diversity at Intel

The Network and Edge group (NEX) at Intel drives the software-defined transformation of the world's infrastructure - in data centers, in networks, and at the edge. We are a team of problem solvers, experimenters, and innovators who are dedicated to designing the network technologies that currently lead and continue to transform data-centre and AI ecosystems.

As a world-class organization, we're looking for outstanding talent to accelerate our growth during an exciting time in Ethernet networking marketing technology. If you're ready to be a part of this journey, then we want to hear from you.

As a Design-Technology Co-Optimization Staff Engineer in NEX, you will:

• Work with leading Intel and industry process technologies as they relate to Intel networking products.
• Analyze the memory (SRAM, RF, CAM, ROM) electrical and layout properties in the Intel process offerings and build core competency to optimize networking/5G/6G products.
• Work with SoC and IP design teams to understand the Area, Power, Performance, Schedule, and Cost metrics needed to make the product compelling and translate them to process technology requirements.
• Partner with tools, library, fabrication, and manufacturing teams to optimize the process to meet product specifications.
• Resolve prototype issues and determine whether problems are design or process-related.
• Conduct experiments to identify potential challenges in the process, ensure that the process meets yield, quality, and reliability standards, and drive continuous improvements to enhance the designs, materials, and methodologies.
• Design, validate, and characterize analog building block devices and template cells.
• Lead the dissemination of process information to design groups, ensure that it meets future product requirements, and extract necessary technical and device performance data for IP and SoC designs.
• Work on engineering challenges and determine trade-offs to get the best course of action.

The Memory DTCO Staff Engineer should possess the following attributes in addition to the qualifications listed below.

• Willingness to mentor team members and lead projects.
• Willingness to work with a global team that will require evening and off-hours engagement with customers and stakeholders.
• Should be a self-starter, able to drive tasks to closure.
The candidate should have strong communication, problem-solving, and analytical skills.

Qualifications

What we need to see (Minimum Qualifications):

• Candidate must have a Bachelor's degree in Electrical Engineering, Computer Engineering or related field and 4+ years of relevant experience OR Master's Degree with a course or research concentration in areas of semiconductor memory process and design and their co-optimization and 3+ years’ experience OR PhD and 1+ years relevant experience.
• 1+ years' experience with process collateral and its implications to memory design and/or manufacturing (yield, process targeting, ...)
• 1+ years' experience with scripting/coding skills and usage of standard tools for data analysis/charting.

How to Stand out (Preferred Qualifications):

• Semiconductor industry experience or has worked on a design project in the industry.
• Exposure to and/or experience with industry simulation and design tools.

Amazing Benefits!

Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel’s benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits

Requirements listed would be obtained through a combination of industry-relevant job experience, internship experiences, and or schoolwork/classes/research.

Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Other Locations

US, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00

• Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

JobType

Hybrid