Lead Mask/Layout Design Tech

Join the engineering team at Honeywell that designs,verifies, integrates, and tests complex integrated circuit products that enablesystems development for deployment in space. Honeywell's integrated circuitwafer foundry produces parts for satellites, space probes, defense, and othernovel applications.  You will develop radiationhardened ASIC Design platform capabilities in support of the organization'sbusiness strategies. You will be responsible for interfacing with internal andexternal Honeywell ASIC-capability development teams and translating our mixedsignal designs and digital library cells using Cadence and Mentor tools forphysical design and verification. You will work closely with world classhardware and mixed signal-ASIC tool flow development engineers during planning,requirements and architecture, design, test, and integration phases. 

Key Responsibilities

• Deliver high quality layout that conform to all design requirements
  
• Provide accurate scheduling and planning to meet project milestone deadlines
  
• Design reviewing and analyzing floor-plans with the circuit designer
  
• Negotiate layout tradeoffs with the circuit designer
  
• Be able to recognize issues in schematic or layout and work with engineers to resolve
  
• Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
  
• Run all verifications including DRC, LVS, ERC, ANTENNA, etc.
  
• Support and assist in tape out, mask generation and orders
  
• Support tool and process enhancements as needed to ensure successful design fabrication
  
• Prepare Documentation
  
• Mentor and Lead and mentor all aspects of our mask design process for assigned programs and to contribute as a SME to other programs and engineers as needed.
  

Tools We Use:

• Cadence PDK and Siemens-EDA physical verification for library item development
  
• Synopsys place-and-route system suite of tools

U.S. PERSON REQUIREMENTS

Due to compliance with U.S. export control laws and regulations, candidate must be a U.S. Person, which is defined as, a U.S. citizen, a U.S. permanent resident, or have protected status in the U.S. under asylum or refugee status.

YOU MUST HAVE

• Bachelors degree in Electrical Engineering or similar field
• 5 years of experience in with Cadence and Mentor/Siemens tools
• Ability and willingness to work on-site at the Honeywell Plymouth, MN facility 3 days per week (possible on-site in Redmond WA, 3+)
• US Citizenship is required

WEVALUE

• Experience in cell design layout and verification for ASIC library utilization
• Experience or interest in memory design layout and verification
• I/O layout design experience and ESD design experience or interest
• Knowledge of Linux OS, scripting languages such as Perl

Additional Information

• Category: Engineering
• Location: 12001 State Highway 55, Plymouth, MN 55441 USA
• Nonexempt
• Due to US export control laws, must be a US citizen, permanent resident or have protected status.