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Form of workFor nearly four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for an award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement and delivering enjoyable employee experiences at every turn. But we couldn't do it without our extraordinary workforce – and that's where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!
We are seeking creative and hardworking engineers interns to join our outstanding Analog/Mixed-Signal Verification, Modeling and Methodology Team. You will collaborate with systems and design teams to facilitate tops down design methodology through the development and validation of System Verilog (SV) models. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. Additionally, we are seeking innovative individuals who are interested in this position which will play a vital role streamlining development methodology for our organization. We are proud of our exceptional environment and multi-faceted culture. Join us and be part of our journey, innovating incredible technology on a global basis!
Responsibilities:- You will contribute to a team that performs verification planning and AMS simulation on full custom ASICs for audio processing applications
- Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types(sv-udt), & Verilog AMS
- Independent Interpretation of analog circuit schematics into abstract models
- Performing regression debug support and other flow/infrastructure development
- Bachelors or higher in Electrical Engineering or Computer Engineering
- Good understanding of analog integrated circuit design
- Organized and detailed with strong communication skills
- Possess outstanding analytical and problem-solving skills
- Results-oriented and ability to operate in dynamic environment
- Python skills would be highly desirable
- Experience with System Verilog real number modeling (RNM) Modeling and/or Verilog-A behavioral modeling
This opportunity is available for the summer semester only. It is available only to students currently enrolled in a MS or PhD program in Electrical Engineering maintaining a GPA of 3.6 or above, and who will be returning to school for at least one semester following completion of his/her internship. Candidate must be available for full-time employment during the internship.
Diversity drives innovation at Cirrus Logic. Different approaches, ideas and points of view are both valued and respected, and employees are rewarded for their skills, experience and performance. Additionally, Cirrus Logic is an Equal Opportunity/Affirmative Action Employer, and we do not discriminate on the basis of race, color, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, gender identity, genetic information or any other characteristic protected by law.
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