Job Description
Positions: ASIC/FPGA Design Verification Engineer with UVM
Location: REMOTE
Duration: 06 Months
Shift: 07:00AM to 04:00PM
Analyzes customer and system requirements to develop basic architectural approaches and detailed specifications for various electronic products. Develops high-level and detailed designs consistent with requirements and specifications. Validates designs through various methods of review, testing and analysis. Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements. Supports Supplier Management with make/buy recommendations and other technical services of limited scope. Provides engineering support throughout the lifecycle of the product. Investigates emerging technologies to develop concepts for future product designs to meet projected requirements. Works under general direction.
Required Skills:
" 5+ years of experience
" 1-2 years of UVM tool
" Cadence Xcelium verification tool
Education: Must have min Bachelor s in Engineering.
Additional Details: Must have min 5 years of experience, UVM experience is important and required.
Location: REMOTE
Duration: 06 Months
Shift: 07:00AM to 04:00PM
Analyzes customer and system requirements to develop basic architectural approaches and detailed specifications for various electronic products. Develops high-level and detailed designs consistent with requirements and specifications. Validates designs through various methods of review, testing and analysis. Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements. Supports Supplier Management with make/buy recommendations and other technical services of limited scope. Provides engineering support throughout the lifecycle of the product. Investigates emerging technologies to develop concepts for future product designs to meet projected requirements. Works under general direction.
Required Skills:
" 5+ years of experience
" 1-2 years of UVM tool
" Cadence Xcelium verification tool
Education: Must have min Bachelor s in Engineering.
Additional Details: Must have min 5 years of experience, UVM experience is important and required.