Job description
Once you understand the details of design components and any associated system reference models. You will construct detailed test plan for various components of the design including use cases, through collaborative work with cross-functional teams. You will create coverage driven verification plans from specifications, review with multi-functional teams and refine to achieve coverage targets. Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and reference models. Work closely with DV methodology architects to improve verification flow. Execute test plan from RTL simulation bring-up to sign-off, report and debug failures, maintain regressions, report verification progress against test plan and coverage metrics.
Address
Sunnyvale, CA
