Address
Form of work- Create UVM simulation plan from design specification.
- Create or modify UVC, Score Board, Monitor, and test cases.
- Verify until functional coverage and code coverage meet project threshold.
- Document results.
Requirements:
Basic Qualifications (Required Skills/Experience):
- 5+ years of experience
- 1-2 years of UVM tool
- Cadence Xcelium verification tool
- As an equal opportunity employer, ICONMA prides itself on creating an employment environment that supports and encourages the abilities of all persons regardless of race, color, gender, age, sexual orientation, citizenship, or disability.
- (ASIC OR "APPLICATION-SPECIFIC INTEGRATED CIRCUIT" OR "APPLICATION SPECIFIC INTEGRATED CIRCUIT" OR "FIELD PROGRAMMABLE GATE ARRAY" OR FPGA) AND (VERIFICATION) AND ("UNIVERSAL VERIFICATION METHODOLOGY" OR "UNIVERSAL VERIFICATION METHODOLOGIES" OR UVM OR UVMS)
