Verification Engineer

Requirements

SKILLS:

Critical:

• Verilog/vhdl
• experience with .LIB modeling and Liberty timing models
• experience with IBIS models
• Scripting (at least python; TCL, SKILL or OCEAN are bonus)

Nice to have:

• Can read Schematics
• SPICE simulation expérience (AFS/Spectre/HSpice) etc.
• experience with Digital synthesis and compilers
• Generating LEF’s

Job Types: Full-time, Contract

Pay: $31.00 - $33.00 per hour

Schedule:

• Monday to Friday

Experience:

• Verilog/vhdl: 2 years (Preferred)
• .LIB modeling and Liberty timing models: 3 years (Preferred)
• IBIS models: 3 years (Preferred)
• Scripting (like python; TCL, SKILL or OCEAN): 2 years (Preferred)
• SPICE simulation (AFS/Spectre/HSpice) etc: 2 years (Preferred)
• Digital synthesis and compilers: 2 years (Preferred)
• Generating LEF’s: 1 year (Preferred)

Work Location: Remote