Job description
- Understand details of microarchitecture and build block / chip level testbench using best-in-class verification methodology. - Create verification plan from specification and in coordination with architects. - Generate directed and ingenuous constrained random tests. - Create/analyze coverage model and enhance testbench/test to increase coverage. - Build automated flows for block and chip level verification. - Debug failures, manage bug tracking, and close coverage. - Hold detailed verification reviews and set standard for coding quality. - Work closely with team members to improve methodology and flow.
Address
Sunnyvale, CA
