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Job Description:
Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
Join the Power Management Controller (PMC) IP team! We are responsible for testing the chip during pre-silicon to make sure we deliver quality products for multiple segments at Intel.
Who You Are
Power Management Controller (PMC) IP team is looking for a Firmware Verification Engineer to join the exciting world of pre-silicon embedded Firmware Verification, working on innovative designs that service multiple Intel product roadmaps.
Responsibilities:
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must have a Bachelor's degree in Electronic Engineering, Computer Engineering, or similar field with 4+ years of experience; OR a Master's degree in Electronic Engineering, Computer Engineering, or similar field with 3+ years experience in the following:
Preferred Qualifications:
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
US, California, Santa Clara
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$144,501.00-$217,311.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description:
Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
Join the Power Management Controller (PMC) IP team! We are responsible for testing the chip during pre-silicon to make sure we deliver quality products for multiple segments at Intel.
Who You Are
Power Management Controller (PMC) IP team is looking for a Firmware Verification Engineer to join the exciting world of pre-silicon embedded Firmware Verification, working on innovative designs that service multiple Intel product roadmaps.
Responsibilities:
- Creating test collateral, environments, and strategies for verifying embedded firmware in the IP team.
- Communicating and collaborating with firmware developers and verification peers.
- Debugging, determining root cause, and fixing failures in existing and new infrastructure, firmware, and software tools.
- Experimentally exploring feature ideas through modeling, simulation, and data analysis.
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications:
Candidate must have a Bachelor's degree in Electronic Engineering, Computer Engineering, or similar field with 4+ years of experience; OR a Master's degree in Electronic Engineering, Computer Engineering, or similar field with 3+ years experience in the following:
- Software/Firmware development
- Reading and interpreting architecture specs
- Verification methodologies
Preferred Qualifications:
- Platform Power Management Flows
- Embedded Software Verification
- Advanced Object Oriented Programming and SW development (design patterns, algorithms, TDD, unit testing)
- Debugging firmware or Register Transfer Level (RTL) code
- Experience in operating system architecture such as memory management IPC scheduling task switching concurrent memory access event driven programming.
- Understanding of design ideas for distributed system and architecture, including but not limited to service-oriented, asynchronous, scalable SW stacks
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
US, California, Santa Clara
Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$144,501.00-$217,311.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
